Digital System Design 4
Digital System Design 4
Lecture 8 – Processor Architecture 1
Computer Architecture
Dr Chang Liu
Course Outline
Week Lecture Topic Chapter Tutorial
1 1 Introduction
1 2 A Historical Perspective
2 3 Modern Technology and Types of Computer
2 4 Computer Perfomance 1
3 5 Digital Logic Review C
3 6 Instruction Set Architecture 1 2
4 7 Instruction Set Architecture 2 2
4 8 Processor Architecture 1 4
5 9 Instruction Set Architecture 3 2
5 10 Processor Architecture 2 4
Festival of Creative Learning
6 11 Processor Architecture 3 4
6 12 Processor Architecture 4 4Processor Architecture 1 – Chang Liu 2
This Lecture
• What does a processor have to do?
• The basic functional blocks of a simple
processor
• Chapter 4.1-4.3
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What does a processor have to do?
• Run our programs!
• More specifically:
– Get the instructions that make up our program, in order
– Decide what each instruction means
– If data is in registers, access the right registers
– If the operation is arithmetic, do the calculation
– If the operation deals with main memory, load/store the
right data in the right place
– If we need to, store result back into registers
– If our program branches, change where we get the next
instruction from
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Processor Lectures
• We will examine two MIPS implementations
– A simplified version
– A more realistic pipelined version
• Simple subset, shows most aspects
– Memory reference: lw, sw
– Arithmetic/logical: add, sub, and, or, slt
– Control transfer: beq, j
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The Big Picture
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• What do the elements look like in the processor?
• How does the datapath flow through the elements?
CPU Overview
add $t0, $s1, $s2
lw $t0, 32($s3)
sw $t0, 32($s3)
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Instruction Execution
• PC instruction memory, fetch instruction
• Register numbers register file, read registers
• Depending on instruction class
– Use ALU to calculate
• Arithmetic result
• Memory address for load/store
• Branch target address
– Access data memory for load/store
– PC target address or PC + 4
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Multiplexers
• Can’t just join wires
together
– Use multiplexers
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Control
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Logic Design Basics
• Information encoded in binary
– Low voltage = 0, High voltage = 1
– One wire per bit
– Multi-bit data encoded on multi-wire buses
• Combinational element
– Operate on data
– Output is a function of input
• State (sequential) elements
– Store information
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Combinational Elements
• AND-gate
Y = A & B
A
B
Y
I0
I1
Y
M
u
x
S
• Multiplexer
Y = S ? I1 : I0
A
B
Y+
A
B
YALU
F
• Adder
Y = A + B
• Arithmetic/Logic Unit
Y = F(A, B)
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Sequential Elements
• Register: stores data in a circuit
– Uses a clock signal to determine when to update
the stored value
– Edge-triggered: update when Clk changes from 0
to 1
D
Clk
Q
Clk
D
Q
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Sequential Elements
• Register with write control
– Only updates on clock edge when write control
input is 1
– Used when stored value is required later
D
Clk
Q
Write
Write
D
Q
Clk
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Clocking Methodology
• Combinational logic transforms data during
clock cycles
– Between clock edges
– Input from state elements, output to state
element
– Longest delay determines clock period
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Building a Datapath
• Datapath
– Elements that process data and addresses
in the CPU
• PC, Registers, ALUs, mux’s, memories, …
• We will build a MIPS datapath incrementally
– Refining the overview design
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Building it Up: Instruction Fetch
1. “Get the instructions that make up our program, in order”
2. “If our program branches, change where we get the next
instruction from”
• We need a block of ROM* to hold the program
• We need to provide an address to ROM and get back data
– this data is the instruction we’ll be executing
• Need a register to store current address
– Program Counter (PC)
• Some architectures make the PC accessible like all of the other data
registers
– Can load/store PC to main memory, making call/return simple
– Can do arbitrary arithmetic for calculating branch offsets using regular ALU…
* This could be RAM, but we’re not going to write to it while we’re running the code –no self-modifying code please!
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Instruction Fetch
32-bit
register
Increment by
4 for next
instruction
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Architectures
• Von Neumann: Same memory for
programs and data
• Harvard: Separate memory for
programs and data
• Modified Harvard:
– Use the same physical memory for data
and program (same chips, bus, etc)
– Still use separate datapaths
– (Separate data/instruction caches)
– Agree that the memory used for
program is read-only and the memory
used as data is read-write
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R-Format Instructions
• Read two register operands
• Perform arithmetic/logical operation
• Write register result
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Load/Store Instructions
• Read register operands
• Calculate address using 16-bit offset
– Use ALU, but sign-extend offset
• Load: Read memory and update register
• Store: Write register value to memory
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Composing the Elements
• Each datapath element can only do one
function at a time
– Hence, we need separate instruction and data
memories (why not Von Neumann Archeciture)
• Use multiplexers where alternate data sources
are used for different instructions
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R-Type/Load/Store Datapath
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lw $t0, 1200($t1)
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add $t0,$s2,$t1
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sw $t0, 1200($t1)
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Next Lecture
• Addressing modes for MIPS
• RSIC & CSIC
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