Digital System Design 4
Digital System Design 4
Lecture 10 – Processor Architecture 2
Computer Architecture
Dr Chang Liu
Course Outline
Week Lecture Topic Chapter Tutorial
1 1 Introduction
1 2 A Historical Perspective
2 3 Modern Technology and Types of Computer
2 4 Computer Perfomance 1
3 5 Digital Logic Review C
3 6 Instruction Set Architecture 1 2
4 7 Instruction Set Architecture 2 2
4 8 Processor Architecture 1 4
5 9 Instruction Set Architecture 3 2
5 10 Processor Architecture 2 4
Festival of Creative Learning
6 11 Processor Architecture 3 4
6 12 Processor Architecture 4 4Processor Architecture 2 – Chang Liu 2
This Lecture
• Branch datapath
• Main control unit
• ALU control
• Build up datapath with control
Processor Architecture 2 – Chang Liu 3
Reminder of Branch Instructions
op
op
op
rs rt rd sa funct
rs rt immediate
jump target
3 Instruction Formats: all 32 bits wide
R format
I format
J format
• Instructions that branch
– beq, bne e.g. $s1, $s2, 25
– j e.g. j 2500
Processor Architecture 2 – Chang Liu 4
Branch Instructions
• Read register operands
• Compare operands
– Use ALU, subtract and check Zero output
• Calculate target address
– Sign-extend displacement
– Shift left 2 places (word displacement)
– Add to PC + 4
• Already calculated by instruction fetch
Processor Architecture 2 – Chang Liu 5
Branch Instructions
Just
re-routes
wires
Sign-bit wire
replicated
Processor Architecture 2 – Chang Liu 6
Full Datapath (without control)
Processor Architecture 2 – Chang Liu 7
Building it Up: Controller
• If we are clever, we can design the instructions so that we
extract bits from the instructions and use these as the
controls signals
– Actually: have to do this in stages
– Pull out some bits (Opcode), use this as control for a MUX which
chooses other instruction bits to become the controls…
• ‘Micro-code’ processors have (effectively) another
processor in here to control the control signals (!)
– The code for this control signal generating processor is called
micro-code and is stored in protected firmware on the CPU
– Means CPU can be ‘reprogrammed’ to handle new instructions
– Could be used for emulation (but isn’t)…
Processor Architecture 2 – Chang Liu 8
The Main Control Unit
• Control signals derived from instruction
0 rs rt rd shamt funct
31:26 5:025:21 20:16 15:11 10:6
35 or 43 rs rt address
31:26 25:21 20:16 15:0
4 rs rt address
31:26 25:21 20:16 15:0
R-type
Load/
Store
Branch
opcode always
read
read,
except
for load
write for
R-type
and load
sign-extend
and add
Processor Architecture 2 – Chang Liu 9
Datapath With Control
Processor Architecture 2 – Chang Liu 10
R-Type Instruction
op rs rt rd sa funct R format
31:26 25:21 20:16 15:11 10:5 5:0
Processor Architecture 2 – Chang Liu 11
Datapath With Control
Processor Architecture 2 – Chang Liu 12
Load Instruction
op rs rt immediate I format
31:26 25:21 20:16 15:0
Processor Architecture 2 – Chang Liu 13
Datapath With Control
Processor Architecture 2 – Chang Liu 14
Branch-on-Equal Instruction
op rs rt immediate I format
31:26 25:21 20:16 15:0
Processor Architecture 2 – Chang Liu 15
Implementing Jumps
• Jump uses word address
• Update PC with concatenation of
– Top 4 bits of old PC
– 26-bit jump address
– 00
• Need an extra control signal decoded from
opcode
2 address
31:26 25:0
Jump
Processor Architecture 2 – Chang Liu 16
Datapath With Control
Processor Architecture 2 – Chang Liu 17
Datapath With Jumps Added
op jump target J format
31:26 25:0
Processor Architecture 2 – Chang Liu 18
Main Control
Processor Architecture 2 – Chang Liu 19
Mapping The Main Control Function to Gates
Processor Architecture 2 – Chang Liu 20
Mapping The Main Control Function to Gates
Processor Architecture 2 – Chang Liu 21
ALU Control
Processor Architecture 2 – Chang Liu 22
Abstracted 32-Bit ALU
• Final 32-Bit ALU
Processor Architecture 2 – Chang Liu 23
ALU Control
• Assume 2-bit ALUOp derived from opcode
– Combinational logic derives ALU control
opcode ALUOp Operation funct ALU function ALU control
lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111
Processor Architecture 2 – Chang Liu 24
Implementing Combinational Control Units
Operation2 =1
Processor Architecture 2 – Chang Liu 25
Mapping the ALU Control Function to Gates
Processor Architecture 2 – Chang Liu 26
Mapping the ALU Control Function to Gates
Processor Architecture 2 – Chang Liu 27
Mapping the ALU Control Function to Gates
Processor Architecture 2 – Chang Liu 28
Memory and Registers
Processor Architecture 2 – Chang Liu 29
ALU and Adders
Processor Architecture 2 – Chang Liu 30
Multiplexers (Data Selectors)
Processor Architecture 2 – Chang Liu 31
Sign Extension
Processor Architecture 2 – Chang Liu 32
Control System
Processor Architecture 2 – Chang Liu 33
You Can Now Design and Build a Simple CPU
Processor Architecture 2 – Chang Liu 34
Next Lecture
• A More Complex CPU
• Pipelining
• Hazards
Processor Architecture 2 – Chang Liu 35