CS 2204: Digital Circuits
Lecture 17
New spec.
We will now discuss a general method to design sequential
circuits from a “specification”
Example: Car speed-limiter
w = 0 if below_limit,
1 if above limit.
Speed limiter
z = 0 no break,
1 apply break.
IMMEDIATELY Apply break if car
exceeds speed-limit for two
consecutive intervals
Timing diagram
Previously, brake applied after two consecutive w=1
Now, we want brake applied immediately!
Moore Vs. Mealy machines
Moore Machine: output depends
only on the current state
We cant use a Moore
machine for immediate
braking!
Mealy Machine: output depends
on current state AND input.
Each edge has an
associated output
value!
State transition diagram for mealy machine
Two One Apply_Break
START
w=1/z=0 w=1/z=1 w=1/z=1
w=0/z=0
w=0/z=0
w=0/z=0
A further simplification
Two One Apply_Break
START
w=1/z=0 w=1/z=1 w=1/z=1
w=0/z=0
w=0/z=0
w=0/z=0
MERGE THESE TWO STATES!
Simplified state transition graph
A
(y=0)
B
(y=1)
START
w=1/z=0 w=1/z=1
w=0/z=0
w=0/z=0
Practice
Module pattern (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg y, Y;
parameter A=1’b0, B =1’b1;
always @(w,y)
case (y)
A: if(w==1’b1) Y = B;
else Y = A;
B: ….
endcase
Always @(negedge Resetn, posedge Clock)
if (Resetn==0) y<=A;
else y <= Y;
//Define output
assign z = (y==B)&(w==1)
endmodule
WHAT CHANGES?
Next state table for mealy model
After State
Assignment
Next state and output logic
Y = w
z = w.y
Draw a circuit diagram for the
Mealy speed limiter
Timing diagram
“serial “ adder
We saw the design of “n-bit” adders previously. These are
combinational adders that take n-bit inputs and output an
(n+1)-bit result all at once.
How many FAs are needed for an n-bit adder?
An alternative is to design a “serial” adder. Pairs of bits
are input serially (one pair in each clock cycle), starting
with the LSBs. The output appears after n clock cycles.
Moore type serial adder
Example:
A = 1 0 1 0
B + 1 1 1 1
---------------------
S = ? ? ? ?
Bits of A and B will arrive at the
input of the FSM immediately after
a positive clock edge
After t=1
Example:
A = 1 0 1 0
B + 1 1 1 1
---------------------
S = ? ? ? ?
0
1
1
0
0
0
Note at this point outputs are
initialized to 0, but we don’t
care about their values for now
After t=2
Example:
A = 1 0 1 0
B + 1 1 1 1
---------------------
S = ? ? ? ?
1
1
0
1
1
0
Note at this point outputs are
initialized to 0, but we don’t
care about their values for now
After t=3
Example:
A = 1 0 1 0
B + 1 1 1 1
---------------------
S = ? ? 0 1
0
1
0
1
0
1
Note at this point outputs are
initialized to 0, but we don’t
care about their values for now
After t=4
Example:
A = 1 0 1 0
B + 1 1 1 1
---------------------
S = ? ? ? ?
1
1
?
?
?
?
Note at this point outputs are
initialized to 0, but we don’t
care about their values for now
Verilog implementation
Module adder (Clock, Resetn, a, b, s);
input Clock, Resetn, a, b;
output s;
reg [1:0] y, Y;
//No longer need a parameter statement
always @(a,b,y)
….
Always @(negedge Resetn, posedge Clock)
if (Resetn==0) y<=A;
else y <= Y;
//Define output
….
endmodule
Mealy implementation of serial adder
Module adder (Clock, Resetn, a, b, s);
input Clock, Resetn, a, b;
output s;
reg [1:0] y, Y;
//No longer need a parameter statement
always @(a,b,y)
….
Always @(negedge Resetn, posedge Clock)
if (Resetn==0) y<=A;
else y <= Y;
//Define output
….
endmodule