CS计算机代考程序代写 algorithm CS 2204: Digital Circuits

CS 2204: Digital Circuits

Lecture 20

i/o for the serial adder

Shift register implementation
Shift register behaviour:

– If L=1, then load values
from input R

– Else if E=1, then keep
shifting right and
loading values from w

– Else, hold on to current
state

8-bit serial adder implementation

– When “Load” is 1, inputs A and B are read into SR-A and SR-B.
– When “Load” goes to 0, the serial adder starts shifting bits into SR-Sum
– Once n=8 clock cycles are done, SR-Sum holds the output.

R = A
L = Load
E = 1’b1
w = 0
Q[0] = a

R = x
L = 0
E = “Run”
w = s
Q = Sum

We want the SR-Sum to keep shifting right for n
clocks after Reset transitions to zero. We will keep
track of that using state variable “Run”

Shift register behaviour:

– If L, then load
values from input R

– If E, then keep
shifting right and
loading values from w

– Else, hold on to
current state

Verilog code

//count-down from 8

//E input for sum shift-reg

//instantiate shift-regs

//adder module
always @(QA,QB,y)
{Y,s} <= QA[0]+QB[0]+y; always @(posedge Clock) if (Load==1) y<=0; else y <= Y; //Count FSM always @(posedge clock) if(Load==1) Count<=8; else if (Count > 0)

count <= count-1; else count <= 0; assign Run = |Count; //bitwise OR of bits of Count. Load LoadLoad 0 Load Load 1 2 3 4 5 6 7 Load 1 0 0 0 0 0 0 A 0010 X X X X X X B 0111 X X X X X X y x 0 0 1 1 0 QA 0010 0001 0000 0000 0000 0000 QB 0111 0011 0001 0000 0000 0000 Count x 4 3 2 1 0 0 Run x 1 1 1 1 0 0 Sum xxxx xxxx 1xxx 01xx 001x 1001 1001 A = 0 0 1 0 B + 0 1 1 1 --------------------- S = 1 0 0 1 NOTE: The values in each time period correspond to the values immediately after a positive clock edge! Arbiter FSMs Many people (“devices”) want to use a shared resource, say a phone-booth. But only person can use it at a time. People raise “requests” to a controller FSM that “grants” requests to only one person at any given point. When the person using the phone booth is done, they “deassert” the request signal. The FSM can then grant access to another device. ARbiter FSM If multiple devices request access at the same time, the FSM determines access based on a priority order. Assume device i has greater priority than device j if i