CS 2204: Digital Circuits
Lecture 9
Generic n-bit adder
=0
Signed arithmetic
What about negative numbers?
– Sign magnitude representation
– The most-significant bit (MSB)
is zero for positive numbers and
1 for negative numbers
– The remaining bits indicate the
magnitude
Example
– Write down the numbers 2 and -7
using 6-bit SMR representation.
2 = 000010
-7 = 100111
– What is the minimum number of
bits needed to represent all
integers in range [-7,7]?
– You need 4 bits!
2s complement representation
The SMR representation is super inefficient for arithmetic
operations. Instead the 2s complement representation is very
commonly used in modern computer systems.
MSB multiplied
By negative number!
Interpreting 2s complement
The SMR representation is super inefficient for arithmetic
operations. Instead the 2s complement representation is very
commonly used in modern computer systems.
If MSB (sign bit) is zero, V(B) = M
If MSB (sign bit) is 1, V(B) = -[2^(n-1)-M]
Interpretation of signed numbers
-27 using 2s complement
how many bits do I need?
4 bits: -8 to +7
5 bits: -16 to 15
6 bits: -32 to 31
1 0 0 1 0 1
-32 16 8 4 2 1
-32 + 5
100101 = 1111 100101
Interpretation of signed numbers
What are the values
corresponding to the 2s
complement Boolean numbers:
1010 = -6
11010 = -6
111010 = -6
= -32 + 16 + 8 + 0+2+0
Additions using twos complement
Add the two numbers as if they were regular unsigned values and
ignore carry-out bit from the MSB. What do you observe?
Adding two numbers in 2s complement format yields the result also
in 2s complement format (if we ignore carry-outs from MSBs)!
Dealing with Overflows
Say we want to add -8 + -7. These can be represented as 4-bit 2s
complement numbers. BUT, the result -15 cannot be represented in
4-bits. We call this an “overflow”
How can we detect that overflow has occurred?
– Overflow can only occur when adding two positive numbers or two
negative numbers.
– If the sign of the result is incorrect, then an overflow has
occurred!
Overflow Example
I added two negative numbers and got a positive result. What
happened here? OVERFLOW!
+1
1 0 0 0 = -8
+ 1 0 0 1 = -7
———————–
1 0 0 0 1 = 1 (??!)
Overflow Example
I added two positive numbers and got a negative result. What
happened here? OVERFLOW!
+1 +1
0 1 1 1 = 7
+ 0 0 1 0 = 2
———————–
1 0 0 1 = -7
Overflow Detector
What logic can you
use to detect
overflows?
+1 +1
0 1 1 1 = 7
+ 0 0 1 0 = 2
———————–
1 0 0 1 = -7
+1
1 0 0 0 = -8
+ 1 0 0 1 = -7
———————–
1 0 0 0 1 = 1
Consider the full adder truth table
Overflow
0
0
0
1
1
0
0
0
When does overflow
occur?
When the carry-in
into the MSB column
is not equal to the
carry out!
Overflow Detector
If carry-in into
(n-1)th column is not
equal to its carry
out
+1 +1
0 1 1 1 = 7
+ 0 0 1 0 = 2
———————–
1 0 0 1 = -7
+1
1 0 0 0 = -8
+ 1 0 0 1 = -7
———————–
1 0 0 0 1 = 1
0
0
Subtraction using 2s complement
x-y = x + (-y)
2s complement subtraction is just 2s complement addition with a
negated value. But how do we negate values?
To negate x, invert all its bits and
add +1. Let’s see if this works by
negating +5.
0 1 0 1 = +5
1 0 1 0 = -6
+ 0 0 0 1 = +1
———————–
1 0 1 1 = -5
Another example
1 1 0 1 = -3
0 0 1 0 = +2
0 0 0 1 = +1
———————–
0 0 1 1 = +3
What about -8?
1 0 0 0 = -8
0 1 1 1 = +7
0 0 0 1 = +1
———————–
1 0 0 0 = -8
(what went wrong here?)
Overflow! The result is actually 01000 = +8
Adder/Subtractor unit
Set to 0 for ADD
operation and 1 for
subtract operation
Inverts bits of the
second operand for sub.
operations
Add + 1
for sub.
operations
Adders in verilog
Full Adder using “structural” Verilog
wire z1, z2, z3;
wire c1, c2, c3;
Vectored signals
Much like in C, you can declare an “array” of bits
4 bit vectors/arrays.
Using behavioral specification
n bit vectors/arrays.
Type reg because outputs in always block
32-bit 2s complement
For loops as in C/C++. + operator performs
additions, not “OR”
Directly using +
Performs additions on
unsigned n-bit values
(i.e., standard columnwise
additions)