CS 2204: Digital Circuits
Lecture 4
Endianness and lilliputians
Big endians Little endians
Digital representations of information
Decimal System with base 10:
Binary system with base 2:
Converting from
binary to decimal
Verilog basics
What function does
f implement?
Like a
function
Module
name
Input
/output
ports
Gates can be
specified in
any order
(out,in1, in2)
wire k, g, h; Internal wires
Testing a verilog module
How do you specify the
module inputs and
observe its outputs?
example1
testbench
0->1
1->0
1->0
`timescale 1ns / 1ps
module testbench();
reg xt1, xt2 , st; // “regs” are types of variables
wire ft;
// Instantiation of design.
example1 myexample (xt1,xt2,st,ft);
initial begin // begin simulation
xt1 = 1’b0; // Set xt1 to logic ‘0’
xt2 = 1’b1; //1’b means 1-bit value
st = 1’b1;
#10 // After 10 time units
xt1 = 1’b1; // Set xt1 to logic ‘1’
xt2 = 1’b0;
st = 1’b0;
#10 // After 10 time units
$finish; // finish simulation
end
endmodule
Regs vs. wires
Can be superconfusing, we’ll try to clear this up as we go
along. You’ll find a super helpful resource here:
https://inst.eecs.berkeley.edu/~cs150/Documents/Nets.pdf
A variable is of type “register” (or reg) if it “drives”
something, in this example the input ports of our module.
In contrast, wires are “passive” and used to “connect” two
things.
https://inst.eecs.berkeley.edu/~cs150/Documents/Nets.pdf
What does a “multiplexer” do?
wire k, g, h;
A “MUX” chooses between inputs x1 and x2 based on s
– x1 and x2 are called “data” inputs
– s is a “select” input
– If s=0, the output f=x1; else f=x2
Boolean function represenation of “Mux”
wire k, g, h;
Exercise
Draw a gate-level netlist corresponding to the following
Verilog code. Draw, take a snap-shot of and upload an image
of the netlist to NYUClasses.
wire z1, z1, z3, z4;
Solution
wire z1, z1, z3, z4;
Behavioural verilog
Our previous Verilog example is an example of “structural”
verilog wherein we describe Boolean functions using
connections between logic gates (ie. a physical structure)
Instead, we can describe the MUX using “behavioral” Verilog,
where we describe the behaviour of the module.
Mux in behavioural verilog
Logical AND
Logical ORLogical NOT
“assign” operator performs a continous assignment of the
RHS to the LHS. By continuous we mean, any time any of
the LHS inputs change, the RHS inputs will also change.
Assign operator
Verilog provides many different ways of equating RHS to LHS.
– assign x = y; //Continuous assignment used to model h/w.
You can write this statement once, but every time y
changes, x will change!
– x=y; //”Blocking” assignment similar to s/w. Happens ONCE
and you move on to the next statement. If y changes
subsequently, x will NOT be updated
Another Example
More behavioural constructions
Now use the standar “=”
operator instead of the
assign.
– x=y; //”Blocking”
assignment similar to
s/w. Happens ONCE and
you move on to the next
statement. If y changes
subsequently, x will NOT
be updated
If s equals 0
(exactly like
C/C++)else
Does this work?
More behavioural constructions
Now use the standar “=”
operator instead of the
assign.
– x=y; //”Blocking”
assignment similar to
s/w. Happens ONCE and
you move on to the next
statement. If y changes
subsequently, x will NOT
be updated
If s equals 0
(exactly like
C/C++)else
No. If inputs x1, x2 or s change, f is NOT
re-evaluated.
More behavioural constructions
Now use the standar “=”
operator instead of the
assign.
– x=y; //”Blocking”
assignment similar to
s/w. Happens ONCE and
you move on to the next
statement. If y changes
subsequently, x will NOT
be updated
“Trigger this
code any time
either x1
changes, or x2
changes or s
changes!”
More behavioural constructions
Now use the standar “=”
operator instead of the
assign.
– x=y; //”Blocking”
assignment similar to
s/w. Happens ONCE and
you move on to the next
statement. If y changes
subsequently, x will NOT
be updated
Because “=”
statements cant
“drive” outputs
reg f was NOT needed when we used the “assign” statements because assign statements
“drive” outputs. Similarly not needed for structural statements likes not(f,x)