CS计算机代考程序代写 CS 2204: Digital Circuits

CS 2204: Digital Circuits

Lecture 2

“Pseudocode” for bit counter

How do we
translate this
pseudo-code to
hardware?

What are the states
of the circuit? Initialize B and Load A

If LSB of A is
one, increment
Counter and
shift A right
by 1

Assert Done

ASM

If LSB of A is
one, increment
Counter and
shift A right
by 1

Assert Done

Assign outputs
Perform actions

State Name

Moore Type State

ConditionalsVariable

Mealy Type OutputsAssign outputs
(input dependent)

Always done in a
given state

Not always done in
a given state

ASM

Assert Done
while s=1.

Assign outputs
Perform actions

State Name

Moore Type State

ConditionalsVariable

Mealy Type OutputsAssign outputs
(input dependent)

Always done in a
given state

Not always done in
a given state

Why are we first
shifting right
and then
checking a0?

ASM

Assert Done

Assign outputs
Perform actions

State Name

Moore Type State

ConditionalsVariable

Mealy Type OutputsAssign outputs
(input dependent)

Always done in a
given state

Not always done in
a given state

Answer: this is
hardware!
Everything in a
state happens in
parallel! Impact
of Shift Right
will be apparent
only in the next
clock!

ASM

Assign outputs
Perform actions

State Name

Moore Type State

ConditionalsVariable

Mealy Type OutputsAssign outputs
(input dependent)

Always done in a
given state

Not always done in
a given state

“Control path”
How do we set control
inputs LA, EA, LB, EB?

Single var in each
control box

Same as LB=1

LA

If I am in state S2
then EA=1

If I am in
state S1,
then LB=1.

If I am in state S1,
and s=0, next state
is S1 else next
state is S2 If I am in state

S2 and z=0 and
a0=1 then EB=1

If I am in
state S2
and z=1
then next
state is
S3.

LA

For now assume
set externally

Verilog implementation: DATAPATH

module counter(V,L,E,Clock,Count);
parameter b = 3;
input [b-1:0] V;
input L, E, Clock;
output reg [b-1:0] Count;

always@(posedge Clock)
if(L) Count <= V; else if(E) Count <= Count+1; endmodule Complete Verilog implemementation Next State Module def Sequential Complete Verilog implemementation Outputs Counter Shifter //or you could just do: //counter ct(0,LB,EB,Clock,B); Shift and add multiplier ASM chart datapath