CS 2204: Digital Circuits
Lecture 12
To begin…
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Other important combinational blocks: muxes
2:1 MUX 4:1 MUX
Exercise
Design a module that takes as input X and Y (4-bit unsigned
values) and a ctrl input. The module outputs S = X + Y if
ctrl=0 and !X if ctrl = 1. S is a 4-bit output. You can make
use of a 4-bit adder, MUXes, ands/or/nots.
Muxes in verilog
4:1 mux
//or if(S==2’b00)
//or if(S==2’b01)
//or if(S==2’b10)
Larger MUxes using smaller muxes
“Decoders”
Used to access memory. That is, given the address of a
specific location in memory, set the wire feeding that
location to ‘1’ and all others to zero.
Exercise: Draw a gate level netlist for a decoder
Decoders with “enable”
Setting the “En” input to 0 turns the decoder “off” that is,
all outputs are zero.
Exercise: Gate level netlist of decoder with enable?
Exercise: Verilog for 4-bit decoder with enable
Use behavioural coding style.
module decoder_enable(X, en, Y) begin
input [3:0] X;
input en;
output reg [15:0] Y;
integer i;
always @(X,en)begin
if (en==1’b0)
Y = 8’h0000;
else begin
Y = 8’h0000;
for (i=0; i<16; i=i+1)
if(X==i)
Y[i] = 1’b1;
end
end
endmodule
Larger decoders from smaller decoders
demultiplexers A demultiplexer passes
data input ‘d’ to output
o1 if s=0, and to output
o2 id s=1. The other
output is set to 0.
s
d
o1
o2
0
1
s o1 o2
0 d 0
1 0 d
Design a 1-to-4 DEMUX
using a 2-to-4 decoder.
solution
d
s0
s1
comparator
Check if A>B, A=B, or A
Hint: look at the bits from right to left.
comparator
When is A>B
– If a3 is 1 and b3 is 0; OR
– If a3=b3, and a2 is 1 and b2 is 0; OR
– If a3=b3, a2=b2, and a1 is 1 and b1 is 0; OR
– If a3=b3, a2=b2, a1=b1, and a0 is 1 and b1 is 0.
Circuit diagram
Exercise: Design a comparator using a 4-bit adder
You can use a 4-bit unsigned adder, ands/ors/nots/MUXes.