CS 2204: Digital Circuits
Lecture 19
“serial “ adder
We saw the design of “n-bit” adders previously. These are
combinational adders that take n-bit inputs and output an
(n+1)-bit result all at once.
How many FAs are needed for an n-bit adder?
An alternative is to design a “serial” adder. Pairs of bits
are input serially (one pair in each clock cycle), starting
with the LSBs. The output appears after n clock cycles.
Moore type serial adder
Example:
A = 1 0 1 0
B + 1 1 1 1
———————
S = ? ? ? ?
Bits of A and B will arrive at the
input of the FSM immediately after
a positive clock edge
After t=1
Example:
A = 1 0 1 0
B + 1 1 1 1
———————
S = 1 0 0 1
0
1
1
0
0
0
Note at this point outputs are
initialized to 0, but we don’t
care about their values for now
After t=2
Example:
A = 1 0 1 0
B + 1 1 1 1
———————
S = ? ? ? ?
1
1
0
1
1
0
Note at this point outputs are
initialized to 0, but we don’t
care about their values for now
After t=3
Example:
A = 1 0 1 0
B + 1 1 1 1
———————
S = ? ? 0 1
0
1
0
1
0
1
Note at this point outputs are
initialized to 0, but we don’t
care about their values for now
After t=4
Example:
A = 1 0 1 0
B + 1 1 1 1
———————
S = ? ? ? ?
1
1
?
?
?
?
Note at this point outputs are
initialized to 0, but we don’t
care about their values for now
Verilog implementation module adder (Clock, Resetn, a, b, s);
input Clock, Resetn, a, b;
output s;
reg [1:0] y, Y;
//No longer need a parameter statement
always @(a,b,y)
//{Y[1],Y[0]} = a + b + y[1];
Y = a + b + y[1];
always @(negedge Resetn, posedge Clock)
if (Resetn==0) y<=2’b00;
else y <= Y;
//Define output
assign s = y[0];
endmodule
Mealy implementation of serial adder
module adder (Clock, Resetn, a, b, s);
input Clock, Resetn, a, b;
output s;
reg y, Y;
always @(a,b,y)
{Y,s} <= a+b+y;
always @(negedge Resetn, posedge Clock)
if (Resetn==0) y<=2’b00;
else y <= Y;
endmodule
i/o for the serial adder
Simple shift register
module shift (Clock, Resetn, In, Out);
input Clock, Resetn, In;
output Out;
reg [3:0] Q;
always @(negedge Resetn, posedge Clock) begin
if (Resetn==0) Q<=4’b0;
else begin
Q[3] <= Q[2];
….
end
end
assign Out = Q[3];
endmodule
Shift register with parallel access
A separate “Load (L)” input allows all contents in the shift
register to be loaded simultaneously. The shift register
also allows all values to be read simultaneously.
Verilog for shift register with parallel access
w
L
R
We can also add Resetn if desired.
Let’s add another input to “enable” shifting
Shift register behaviour:
- If L, then load values
from input R
- If E, then keep shifting
right and loading values
from w
- Else, hold on to current
state
8-bit serial adder implementation
- When “Load” is 1, inputs A and B are read into SR-A and SR-B.
- When “Load” goes to 0, the serial adder starts shifting bits into SR-Sum
- Once n=8 clock cycles are done, SR-Sum holds the output.
R = A
L = Load
E = 1’b1
w = x
Q[0] = a
R = x
L = x
E = ?
w = s
Q = Sum
We want the Sum register to keep shifting right for
n clocks after Reset transitions to zero. We will
keep track of that using state variable “Run”
Shift register behaviour:
- If L, then load values from input R
- If E, then keep shifting right and
loading values from w
- Else, hold on to current state
Verilog code
//count-down from 8
//E input for sum shift-reg
//instantiate shift-regs
//adder module
always @(QA,QB,y)
{Y,s} <= QA[0]+QB[0]+y;
always @(posedge Clock)
if (Load==1) y<=2’b00;
else y <= Y;
//Count FSM
always @(posedge clock)
if(Load==1) Count<=8;
else if (Count != 0)
count <= count-1;
assign Run = |Count;
Load
Load
Load
Load
Arbiter FSMs
Many people (“devices”) want to use a shared resource, say a
phone-booth. But only person can use it at a time. People
raise “requests” to a controller FSM that “grants” requests
to only one person at any given point.
When the person using the phone booth is done, they
“deassert” the request signal. The FSM can then grant access
to another device.
ARbiter FSM
If multiple devices request access at the same time, the FSM
determines access based on a priority order. Assume device i
has greater priority than device j if i