CS 2204: Digital Circuits
Lecture 13
Putting it all together
0
Build a smoke alarm that starts
ringing if there is smoke and keeps
ringing till reset is pushed
Ringer remains OFF
when push-button
released
0
00
1
Take home: The smoke detector “remembers” its output
when both inputs are zero!!!
S/R Latch
R (reset)
S (set)
QaQb
*unless S/R were both
previously logic 1
“Gated” SR Latch
Behaves like an S/R latch but has an extra input “G” that
“gates” the latch.
– When G=1, gated S/R latch behaves like a normal S/R latch
– When G=0, the latch is gated, that is, it latches on to
(or remembers) its previous outputs even if S/R change
G
G
Exercise
Add a “gating” input G to the standard S/R latch
Clocks
The G input of an S/R latch is often connected to a clock.
The latch is then referred to as a “clocked” S/R latch
Latch is
“transparent”
Latch is
“opaque”
Timing diagram
Outputs of the
clocked latch
ONLY change when
“Clk” is logic 1!
Clocked “D” Latch
Replaces S and R with a single input D!
Timing diagram
Clocked latches vs. “flip-flops”
Clock latches are “level triggered”
– Allow D to pass to Q (i.e, transparent) when the “level”
of clock Clk=1
– Remembers previous value when Clk=0
Flip-flops are like latches but “edge triggered”
– Allow D to pass to Q only when Clk transitions from logic
0 to logic 1
– Remembers value otherwise
Flip-Flops
A “positive” edge-triggered
flip-flop passes input D to output
Q when Clk transitions from 0->1
A “negative” edge-triggered
flip-flop passes input D to output
Q when Clk transitions from 1->0
– Equivalent to a positive
edge-triggered flip-flop with
a negated clock
Timing diagrams
Building a flip-flop from latches
Leader Follower
Clk
Clk
2
–
b
i
t
A
d
d
e
r
1
0
Assume FF outputs are
initialized to 0
Q0
Q1 S0
S1
Q0=0
Q1=0
S0=1
S1=0
Q0=1
Q1=0
S0=0
S1=1
Q0=0
Q1=1
Binary
Up-Counter
S0=1
S1=1
Q0=1
Q1=1
S0=0
S1=0
Q0=0
Q1=0