CS 2204: Digital Circuits
Lecture 15
Timing diagram
Clocked latches vs. “flip-flops”
Clock latches are “level triggered”
– Allow D to pass to Q (i.e, transparent) when the “level”
of clock Clk=1
– Remembers previous value when Clk=0
Flip-flops are like latches but “edge triggered”
– Allow D to pass to Q only when Clk transitions from logic
0 to logic 1
– Remembers value otherwise
Flip-Flops
A “positive” edge-triggered
flip-flop passes input D to output
Q when Clk transitions from 0->1
A “negative” edge-triggered
flip-flop passes input D to output
Q when Clk transitions from 1->0
– Equivalent to a positive
edge-triggered flip-flop with
a negated clock
Timing diagrams
Building a flip-flop from latches
Leader Follower
Clk
Clk
2
–
b
i
t
A
d
d
e
r
1
0
Assume FF outputs are
initialized to 0
Q0
Q1 S0
S1
Q0=0
Q1=0
S0=1
S1=0
Q0=1
Q1=0
S0=0
S1=1
Q0=0
Q1=1
Binary
Up-Counter
S0=1
S1=1
Q0=1
Q1=1
S0=0
S1=0
Q0=0
Q1=0
We will
See later how
to initialize
Q0 and Q1
Verilog for flip-flops
module dff (D, clk, Q)
input D, clk;
output reg Q;
always @(posedge clk) begin
Q = D;
end
endmodule
CLK
For D
Flip-flops we
Will typically
only keep the
Q output and
drop its
complemented
output
What FOR CASCADED flip flops
module dff (D, clk, Q1, Q2)
input D, clk;
output reg Q;
always @(posedge clk) begin
Q1 = D;
Q2 = Q1;
end
endmodule
D Q1 Q2
clk clk
Does this work?
Before first posedge
module dff (D, clk, Q1, Q2)
input D, clk;
output reg Q;
always @(posedge clk) begin
Q1 = D;
Q2 = Q1;
end
endmodule
D Q1 Q2
clk clk
Assume initial
vals are
Q1 = 0, Q2 = 0
0 0
At first posedge
module dff (D, clk, Q1, Q2)
input D, clk;
output reg Q;
always @(posedge clk) begin
Q1 = D;
Q2 = Q1;
end
endmodule
D Q1 Q2
clk clk
D=1 at first
posedge
0 01
Immediately after first posedge
module dff (D, clk, Q1, Q2)
input D, clk;
output reg Q;
always @(posedge clk) begin
Q1 = D;
Q2 = Q1;
end
endmodule
D Q1 Q2
clk clk
What should Q1 and
Q2 actually be?
1 01
Immediately after first posedge
module dff (D, clk, Q1, Q2)
input D, clk;
output reg Q;
always @(posedge clk) begin
Q1 = D;
Q2 = Q1;
end
endmodule
D Q1 Q2
clk clk
What does the code
do? Does not work
1 11
What went wrong
module dff (D, clk, Q1, Q2)
input D, clk;
output reg Q;
always @(posedge clk) begin
Q1 = D;
Q2 = Q1;
end
endmodule
D Q1 Q2
clk clk
Q1=D gets evaluated
first. Q1 gets a new
value, and this value
is immediately passed
to Q2 when Q2=Q1 is
evaluated!
1 11
But Q2
should be
assigned to
the “old”
value of
Q1….!!
“Non-Blocking” Assignments
module dff (D, clk, Q1, Q2)
input D, clk;
output reg Q;
always @(posedge clk) begin
Q1 <= D; Q2 <= Q1; end endmodule D Q1 Q2 clk clk = is a “blocking” assignment. Statements get evaluated in sequence. 1 01 But <= is a non-blocking assignment. Statement get evaluated in parallel! “Non-Blocking” Assignments module dff (D, clk, Q1, Q2) input D, clk; output reg Q; always @(posedge clk) begin Q1 <= D; Q2 <= Q1; end endmodule D Q1 Q2 clk clk 1 01 All RHS values get evaluate at the positive edge in parallel. Then they are assigned to the LHS together. Immediately after posedge with non-blocking assign module dff (D, clk, Q1, Q2) input D, clk; output reg Q; always @(posedge clk) begin Q1 <= D; Q2 <= Q1; end endmodule D Q1 Q2 clk clk What does the code do? 1 01 Initializing flip-flop values We will use an extra “Resetn” input. A zero value of Resetn input causes the flip-flops output Q to reset to 0 immediately (no waiting for posedge of clock!) This is called an “asynchronous” reset CLK Resetn Implement 2-bit up-counter in verilog module 2bupcount (clk, resetn, Q) input clk, resent; Output reg [1:0] Q; Reg [1:0] S; always @(Q) S = Q+l; always @(negedge resetn, posedge clk) begin if(!resetn) Q <=0; Else Q <= S; end endmodule