CS 2204: Digital Circuits
Lecture 11
Signed adder with overflow and carryout
A signed 2s complement adder is similar to an unsigned
adder, except that it also needs an overflow signal
Concatenation
of bits
Overflow cond
for signed
adds
Adder/Sub
module addsubn (X, Y, ctrl, S, carryout, ov);
//if ctrl=0, then X+Y else X-Y
Parameter n=32
input [n-1:0] X, Y;
input ctrl;
output reg [n-1:0] S;
output reg carryout, overflow;
//Y ^ ctrl =
always @(X,Y,ctrl)
begin
if(ctrl==0) begin
{carrout,S} = X+Y;
overflow = ….;
end
else begin
{carryout,S} = X + (~Y) + 1’b1;
overflow = ….;
end
end
endmodule
Calling a parameterized module
You can call the parameterized adder module from a top level
module by using #() to set the values of the module’s
parameters. For example:
addern #(16) myadder (carryin, X, Y, S);
Setting parameters
Unsigned multiplication
Multiplication with 2
M = [m3,m2,m1,m0]
V(M) = [m3*8 + m2*4 + m1*2 + m0*1]
2*V(M) = 2*[m3*8 + m2*4 + m1*2 + m0*1]
= [m3*16 + m2*8 + m1*4 + m0*2 + 0*1]
HW implementation
Signed mults
Convert any negative operand to a positive value
(recall, by complementing and adding 1), use
unsigned multiplication and finally if one of the
two operands is negative, negate the result!
Other important combinational blocks: muxes
2:1 MUX 4:1 MUX
Muxes in verilog
4:1 mux
//or if(S==2’b00)
//or if(S==2’b01)
//or if(S==2’b10)
Larger MUxes using smaller muxes
“Decoders”
Used to access memory. That is, given the address of a
specific location in memory, set the wire feeding that
location to ‘1’ and all others to zero.
Exercise: Draw a gate level netlist for a decoder
Decoders with “enable”
Setting the “En” input to 0 turns the decoder “off” that is,
all outputs are zero.
Exercise: Gate level netlist of decoder with enable?
Exercise: Verilog for decoder with enable
Use any coding style you’re comfortable with!