CS 2204: Digital Circuits
Lecture 23
“Control path”
How do we set control
inputs LA, EA, LB, EB?
Single var in each
control box
Same as LB=1
LA
If I am in state S2
then EA=1
If I am in
state S1,
then LB=1.
If I am in state S1,
and s=0, next state
is S1 else next
state is S2 If I am in state
S2 and z=0 and
a0=1 then EB=1
If I am in
state S2
and z=1
then next
state is
S3.
LA
For now assume
set externally
Verilog implementation: DATAPATH
module counter(V,L,E,Clock,Count);
parameter b = 3;
input [b-1:0] V;
input L, E, Clock;
output reg [b-1:0] Count;
always@(posedge Clock)
if(L) Count <= V;
else
if(E) Count <= Count+1;
endmodule
Complete Verilog implementation
Next State
Module def
Sequential
Complete Verilog implemementation
Outputs
Counter
Shifter
//or you could just do:
//counter ct(0,LB,EB,Clock,B);
Shift and add multiplier
ASM chart
datapath
Asm with control signals
Long division
pseudocode
(Left-shift R||A)
shifts bits of A into
the R register
Why did we split
these into two
separate states?
Datapath
Exercise: write down
control signals