Description
In our prior assignment we added the data memory (a place we can store large amounts of data, which can later be retrieved). It has one problem though. It’s unrealistic in that we can access this large memory in a single clock.
In this assignment we introduce the concept of stalling the CPU, for multiple clocks, to deal with memory access latency.
Note: This assignment requires importing a Logisim library file. If your prior submission did not work correctly, it needs to be fixed first.
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Outline Steps
Starting from the your solution for prior assignment… 1) Download this Logisim library file.
2) From the top panel of Logisim, choose Project->LoadLibrary->LogisimLibrary, and chose the .circ file you just downloaded. A new circuit group with “StallableMem” should appear in your project.
3) Main Task: Remove the “Data Ram” we added in last assignment, and replace it with this StallableMem. (How do you do this while keeping the code from prior assignment working as before?)
3.a) The clock [IMPORTANT]: You must connect the main clock generator only to the “clock” pin on the new StallableMem. And connect the global clock signal (the one connected everywhere else on CPU) to the “stallable clock” output pin from your StallableMem.
– When the StallableMem”s “Store” or “Select” pins are set high, the “Stallable Clock” is stalled for a number of clocks, By using this clock for the rest of the CPU, we effectively stall the CPU until the data memory says it is ready to proceed.
– You can double click on the counter to see its internals and its state at any point during debug.
– Note: In prior assignments you could have left the “load” pin of the ram always high, and things would worked fine (because the output would just be ignored if not executing a “load” instruction). But with this StallableRam, you need to correctly set the “Select” pin high only when executing data “load” instructions, (determined by your instruction decoder), because that is what tells the ram it needs to fetch an address, and whether it needs to stall the CPU.
4) Connect an Led to the “Stalled” pin of your StallableMem, so we can see when it is stalling the CPU.
The criterion is as in the prior assignment. The Fibo sequence should be first stored to the new data ram in an initial loop, then exit that loop and start retrieving the sequence from data memory and displaying it on the TTY. No code change should be needed if your last assignment worked correctly.
The only difference is that this time I will be checking that the CPU stalls correctly on data memory accesses.
Your submission zip file must contain your circ, a copy of the StallableMem .circ (test that when opened from scratch it finds the library file), your instruction code.
You must not modify the StallableMem. The only exception allowed is modifying the address and data bus widths to match your CPU side, if your prior submissions used larger address or data widths than 8 bits.
Important criterion: The CPU must only stall on data memory reads and writes, nothing else.
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