Chapter 4
MARIE: An Introduction
to a Simple Computer
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Chapter 4 Objectives
• Learn the components common to every modern
computer system.
• Be able to explain how each component
contributes to program execution.
• Understand a simple architecture.
• Understand how assembly language and machine
code relate.
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4.1 Introduction
• Chapter 1 presented a general overview of
computer systems.
• Chapter 2, we looked at how data is stored and
manipulated.
• Chapter 3 described the fundamental
components of digital circuits and how they can
be composed to form larger functional units.
– Combinational Circuits such as the Full Adder
– Flip-flops for storage
– Decoders and Multiplexers
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4.2 CPU Basics
• The computer’s CPU fetches, decodes, and
executes program instructions.
• The two principal parts of the CPU are the data
path and the control unit.
– The data path is responsible for processing and moving of
data around. A data bus connects the ALU and registers
together to allow data to flow between them.
– The control unit arbitrates the various components
connected to the data path.
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• The CPU shares data with other system
components by way of a data bus.
– A bus is a set of wires that simultaneously convey a
single bit along each line.
• Buses consist of:
– data lines: the value that is being moved
– control lines: the direction the data is flowing
– address lines: location information of the data
4.3 The Bus
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4.3 The Bus
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• Different types of buses are found in computer
systems: point-to-point, and multipoint buses.
• Different configurations also exist and control
over the bus needs to be arbitrated.
– Single Master: one device arbitrates all other devices
– Daisy Chain: devices have a known order of priority,
highest goes first
– Centralized Parallel: dedicated logic controls which
device has access
– Distributed w/ self-detection: devices coordinate with
each other to determine access
– Distributed w/ collision detection: devices assume the
bus is free and then stop if an error (collision) occurs.
4.3 The Bus
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4.4 Clocks
• Every computer contains at least one clock that
synchronizes the activities of its components.
• A fixed number of clock cycles are required to carry
out each data movement or computational operation.
• A component can only do one thing per clock cycle.
• Clock cycle time is the reciprocal of clock frequency.
– An 800 MHz clock has a cycle time of 1.25 ns.
– 1 / 800 000 000 Hz = 0.000 000 001 25 s
• The time a program will take to run can be calculated:
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4.5 The Input/Output Subsystem
• A computer communicates with the outside world
through its input/output (I/O) subsystem.
• I/O devices connect to the CPU through various
interfaces.
• I/O can be memory-mapped– where the I/O device
behaves like main memory from the CPU’s point of
view.
• Or I/O can be instruction-based, where the CPU has
a specialized I/O instruction set.
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4.6 Memory Organization
• Computer memory consists of a linear array of
addressable storage cells that are like registers.
• Memory is a group of memory modules (sticks of RAM)
• Each memory module is comprised of several chips.
– A memory module is defined by a length and width
• So, what can a 16MB memory module look like?
– 8M x 16bit or 128 Mbit or 16 MByte
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• Physical memory sometimes consists of more than
one RAM chip.
• Many RAM chips can be grouped
– to increase word size
– to increase addressable space
• Low-order interleaving uses the low order address
bits to select the memory chip
• High-order interleaving uses the high order address
bits to select the memory chip
The next two slides illustrate these two ideas.
4.6 Memory Organization
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4.6 Memory Organization
• Example: Main memory consists of 16 x 2K x 8 bit chips.
– 24 x 211 x 8 bit = 215 bytes
• In high-order interleaving the high-order 4 bits select the chip.
• In low-order interleaving the low-order 4 bits select the chip.
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4.6 Memory Organization
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4.6 Memory Organization
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4.6 Memory Organization
• EXAMPLE 4.1 Suppose we have a 128-word
memory that is 8-way low-order interleaved
– which means it uses 8 memory banks; 8 = 23
• So we use the low-order 3 bits to identify the bank.
• Because we have 128 words, we need 7 bits for
each address (128 = 2 7 ).
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4.7 Interrupts
• Normal program execution can be altered when a
specific event occurs. The CPU is alerted to such an
event through an interrupt.
• Interrupts can be triggered by
– External events such as I/O operations
– Internal events such as arithmetic errors, invalid
instructions, explicit software interrupts
• Each type of interrupt has interrupt handler code that
the CPU executes as soon the the interrupt occurs
and the returns control back to the program as soon
as it has been handled.
• Interrupts run at a higher privilege level on CPUs that
support different privilege levels.
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Questions?
• Functional units from chapter 3 (flip-flops, adders…)
• CPU (datapath, control unit)
• Buses
• Clocks
• I/O
• Memory
• Interrupts
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4.8 MARIE
• We can now bring together many of the ideas that
we have discussed to this point using a very simple
model computer.
• Our model computer, the Machine Architecture that
is Really Intuitive and Easy, MARIE, was designed
for the singular purpose of illustrating basic computer
system concepts.
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The MARIE architecture has the following
characteristics:
• Binary, two’s complement data representation.
• Stored program, fixed word length data and
instructions.
• 4K words of word-addressable main memory.
• 16-bit data words.
• 16-bit instructions, 4 for the opcode and 12 for the
address.
• A 16-bit arithmetic logic unit (ALU).
• Seven registers for control and data movement.
4.8 MARIE
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MARIE’s seven registers are:
– Accumulator, AC, a 16-bit register that holds a
conditional operator (e.g., “less than”) or one operand
of a two-operand instruction.
– Memory address register, MAR, a 12-bit register.
– Memory buffer register, MBR, a 16-bit register .
– Program counter, PC, a 12-bit register.
– Instruction register, IR.
– Input register, InREG, an 8-bit register.
– Output register, OutREG, an 8-bit register.
4.8 MARIE
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This is the MARIE architecture shown graphically.
4.8 MARIE
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• This is the MARIE data
path shown graphically.
– The registers are
interconnected through a
common data bus.
– Each register has a
unique address
– The ALU, the
accumulator and the
memory buffer register
have direct connections
to each other
4.8 MARIE
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• A computer’s instruction set architecture (ISA)
specifies the format of its instructions and the
primitive operations that the machine can perform.
• The ISA is an interface between a computer’s
hardware and its software.
• Some ISAs include hundreds of different instructions
for processing data and controlling program
execution.
• The MARIE ISA consists of only thirteen instructions.
4.8 MARIE
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• This is the format
of a MARIE instruction:
• The fundamental MARIE instructions are:
4.8 MARIE
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• This is a bit pattern for a LOAD instruction as it would
appear in the IR:
• We see that the opcode is 1 and the address from
which to load the data is 3.
4.8 MARIE
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• Each of our instructions consists of a sequence of
smaller instructions called microoperations.
• The exact sequence of microoperations that are
carried out by an instruction can be specified using
register transfer language (RTL).
• In the MARIE RTL, we use the notation M[X] to
indicate the actual data value stored in memory
location X, and to indicate the transfer of bytes to a
register or memory location.
4.8 MARIE
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• The RTL for the LOAD instruction is:
• Similarly, the RTL for the ADD instruction is:
MAR X
MBR M[MAR]
AC AC + MBR
MAR X
MBR M[MAR]
AC MBR
4.8 MARIE
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• Recall that SKIPCOND skips the next instruction
according to the value of the AC.
• The RTL for this instruction is the most complex in
our instruction set:
If IR[11,10] = 00 then
If AC < 0 then PC PC + 1 else If IR[11,10] = 01 then If AC = 0 then PC PC + 1 else If IR[11,10] = 11 then If AC > 0 then PC PC + 1
4.8 MARIE
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4.9 Instruction Processing
• The fetch-decode-execute cycle is the series of steps
that a processor uses to perform instructions
• fetch an instruction from memory, place it into IR.
• decoded the instruction in IR.
– At this point we have decoded steps in the CPU
representing RTL
• execute the decoded steps of the instruction.
– At the end, restart with a fetch for the next instruction
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• Interrupts alter the flow of running code.
• When an interrupt occurs, the CPU…
– finishes running the current instruction
– saves the state of important registers (such as PC)
– sets PC to the ISR and continues from there
• When the interrupt code is done, it calls a return
from interrupt instruction to return control back to
the interrupted code (by restoring PC)
4.9 Instruction Processing
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• For general-purpose systems, it is common to
disable all interrupts during the time in which an
interrupt is being processed.
– Typically, this is achieved by setting a bit in the flags
register.
• Interrupts that are ignored in this case are called
maskable.
• Nonmaskable interrupts are those interrupts that
must be processed in order to keep the system in
a stable condition.
4.9 Instruction Processing
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• Consider the simple MARIE program given below.
We show a set of mnemonic instructions stored at
addresses 0x100 – 0x106 (hex):
4.10 A Simple Program
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• Let’s look at what happens inside the computer when
our program runs.
• This is the LOAD 104 instruction:
4.10 A Simple Program
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• Our second instruction is ADD 105:
4.10 A Simple Program
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4.11 A Discussion on Assemblers
• Machine instructions like 1104 are hard for people
to understand
• Mnemonic instructions, like LOAD 104, are easy for
people to write and understand.
• Assemblers translate mnemonic instructions into
machine instructions
– Assemblers are different from compilers
– There is a one-to-one relationship between mnemonic
instructions and machine instructions.
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• Assemblers create an object program file from
mnemonic source code in two passes.
• During the first pass, the assembler assembles as
much of the program as it can, while it builds a
symbol table that contains memory references for
all symbols in the program.
• During the second pass, the instructions are
completed using the values from the symbol table.
4.11 A Discussion on Assemblers
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• Consider our example
program at the right.
– Note that we have included
two directives HEX and
DEC that specify the radix
of the constants.
• The first pass, creates
a symbol table and the
partially-assembled
instructions as shown.
4.11 A Discussion on Assemblers
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• After the second pass, the
assembly is complete.
4.11 A Discussion on Assemblers
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Questions?
• MARIE (data path, registers and their role)
• Machine code instructions and their format
• Register transfer language
• Fetch Execute Decode
• Interrupts
• Converting from Assembly language to machine
code