UART
Branch and Jump Disassembly
Christopher Mar
Please watch the ”Instruction Breakdown/Datapath Tutorial” video before this lecture. This lecture covers, in more detail, how branch and jump addresses are handled.
PLPTool CPU View Demo
Available in Video Lecture
2
Two’s Complement
Used to represent negative numbers
If most significant bit (MSB) is 0, signed value is positive
Also equivalent to it’s unsigned value
If MSB is a one, signed value is negative
A conversion must be used to determine the magnitude of the number
Converting From Two’s Complement
Flip all bits (bitwise NOT)
Add the value, 1
Example Conversion
4-bit two’s compliment value, 0b1110
Flip bits:
0b0001
Add 1:
0b0010
This is equal to 2 so the 0b1110 is equal to -2
Two’s Complement Table
Bits Signed Value Unsigned Value
011 3 3
010 2 2
001 1 1
000 0 0
111 -1 7
110 -2 6
101 -3 5
100 -4 4
The -1 contains all one’s. As the magnitude of the unsigned number decreases, the signed value becomes more negative.
Assembler Directive: .org
The .org assembler directive indicates where the instructions that follow should be placed in memory
New projects add .org 0x10000000 because this is the first address in RAM
Labels
Pointers to memory locations of instructions
Assembler replaces labels with the address of the instruction being pointed to
RAM Organization
RAM occupies the address range:
0x10000000 to 0x10FFFFFC
0b0001
The first 4 bits of every RAM address are the same
RAM Organization
Memory is byte addressable
Memory addresses are word aligned
A word contains 32-bits (4 bytes)
Each address is a multiple of 4
Two least significant bits of a word aligned address are always zero
Jump Instruction Format
4 most significant bits and 2 least significant bits always the same
Use first 4 bits of previous address
Truncate 2 least significant bits
CPU shifts address left two bits to restore 2 zeroes
opcode
immediate value
6 bits
26 bits
Calculate Jump Address
000010
00000000000000000000000110
6 bits
26 bits
PC = PC[31:28] + (imm << 2) = 0x10000000 + (0b110 << 2) = 0x10000000 + (0b11000) = 0x10000000 + 0x18 = 0x10000018 Jump Instruction Format Branch Instruction Format The value in rs and rt indicate which registers to compare 5 bits can represent the numbers 0 to 31 PLP has 32 registers opcode rs 6 bits 5 bits rt 5 bits offset 16 bits Branch Instruction Format Offset is the signed value Represents the number of instructions from the branch delay slot address to the label address 2 least significant bits of the offset are truncated just as they are for the jump opcode rs 6 bits 5 bits rt 5 bits offset 16 bits Calculate Branch Offset Offset: 0xFFFE is the signed value -2 CPU shifts offset value left 2 bits for address offset Address offset: -8 ( = -2 << 2) Offsets can also be positive if the target label is after the current instruction 000101 01000 opcode rs 00000 rt 1111 1111 1111 1110 offset Branch Offset Advanced Topics Quiz