Chapter 7
Input/Output and
Storage Systems
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7.1 Introduction
• A von Neumann machine has three parts:
– CPU, Memory, Input/Output
• Data storage and retrieval is one of the primary
functions of computer systems.
– One could easily make the argument that computers are
more useful to us as data storage and retrieval devices than
they are as computational machines.
• All computers have I/O devices connected to them
– For good performance, I/O should be kept to a minimum.
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7.2 I/O and Performance
• Sluggish I/O throughput can have a ripple effect,
dragging down overall system performance.
– This is especially true when virtual memory is involved.
• The fastest processor in the world is of little use
if it spends most of its time waiting for data.
• If we really understand what’s happening in a
computer system, we can make the best
possible use of its resources.
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7.4 I/O Architectures
• We define input/output as a subsystem of
components that moves coded data between
external devices and a host system.
• I/O subsystems include:
– Blocks of main memory that are devoted to I/O functions.
– Buses that move data into and out of the system.
– Control modules in the host and in peripheral devices
– Interfaces to external components such as keyboards and
disks.
– Cabling or communications links between the host system
and its peripherals.
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This is a
model I/O
configuration.
7.4 I/O Architectures
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• I/O can be controlled in five general ways.
– Programmed I/O reserves a register for each I/O
device. Each register is continually polled to detect
data arrival.
– Interrupt-Driven I/O allows the CPU to do other things
until I/O is requested.
– Memory-Mapped I/O shares memory address space
between I/O devices and program memory.
– Direct Memory Access (DMA) offloads I/O processing
to a special-purpose chip that takes care of the details.
– Channel I/O uses dedicated I/O processors.
7.4 I/O Architectures
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This is an idealized I/O subsystem that uses interrupts.
Each device connects its interrupt line to the interrupt controller.
The controller
signals the
CPU when any
of the interrupt
lines are
asserted.
7.4 I/O Architectures
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• The status of the interrupt signal is checked at the
top of the fetch-decode-execute cycle.
• The code that is executed whenever an interrupt
occurs is determined by a set of addresses called
interrupt vectors that are stored in low memory.
• The system state is saved before the interrupt
service routine is executed and is restored
afterward.
7.4 I/O Architectures
We provide a flowchart on the next slide.
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7.4 I/O Architectures
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• In memory-mapped I/O, devices and main memory
share the same address space.
– Each I/O device has its own reserved block of memory.
– Memory-mapped I/O therefore looks just like a memory
access from the point of view of the CPU.
– The same instructions to move data to and from both I/O
and memory, greatly simplifying system design.
• In small systems the low-level details of the data
transfers are offloaded to the I/O controllers built
into the I/O devices.
7.4 I/O Architectures
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This is a DMA
configuration.
Notice that the DMA
and the CPU share the
bus.
The DMA runs at a
higher priority and
steals memory cycles
from the CPU.
7.4 I/O Architectures
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• Character I/O devices process one byte (or
character) at a time.
– Examples include modems, keyboards, and mice.
– Keyboards are usually connected through an interrupt-
driven I/O system.
• Block I/O devices handle bytes in groups.
– Most mass storage devices (disk and tape) are block I/O
devices.
– Block I/O systems are most efficiently connected through
DMA or channel I/O.
7.4 I/O Architectures
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• I/O buses, unlike memory buses, operate
asynchronously. Requests for bus access must
be arbitrated among the devices involved.
• Bus control lines activate the devices when they
are needed, raise signals when errors have
occurred, and reset devices when necessary.
• The number of data lines is the width of the bus.
• A bus clock coordinates activities and provides
bit cell boundaries.
7.4 I/O Architectures
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This is a generic DMA configuration showing how the DMA
circuit connects to a data bus.
7.4 I/O Architectures
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This is how a bus connects to a disk drive.
7.4 I/O Architectures
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Timing
diagrams,
such as this
one, define
bus
operation in
detail.
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• All modes only transfer streams or blocks of bits
• Serial data transmission
– Requires only one conductor
– Less prone to synchronization errors
• Data can travel further
– More complex to implement
• Parallel data transmission
– Requires one conductor for each bit.
• Signal lines also need their own conductor.
• Parallel cables are fatter than serial cables.
– Simple to implement, all bits per word are present at the
same time.
7.5 Data Transmission Modes
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7.5 Data Transmission Modes
• Bytes can be conveyed from one point to another
by sending their encoding signals simultaneously
using parallel data transmission or by sending
them one bit at a time in serial data transmission.
– Parallel data
transmission
for a printer
resembles the
signal protocol
of a memory
bus:
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• Input/Output
• Performance
• I/O Subsystems
• Memory Mapped I/O
• Interrupt driven I/O
Questions?