Week 2 — Thu July 8
Single Cycle Processor
CSE-141 Summer Session I 2021
Many slides adapted from Dean Tullsen
Administrative
• Homework 1 is due tonight
• Homework 2 will be posted tonight
• Due next Thursday 11:59 pm
Previously on CSE-141…
Computer Architecture
Computer Architecture =
Instruction Set Architecture
+
Machine Organization
Computer Architecture
Computer Architecture =
Instruction Set Architecture
+
Machine Organization
How you talk to the machine
Computer Architecture
Computer Architecture =
Instruction Set Architecture
+
Machine Organization
What the machine hardware looks like
How you talk to the machine
The Big Picture: The Performance Perspective
• Processor design (datapath and control) will determine:
– Clock cycle time
– Clock cycles per instruction
• Starting today:
– Single cycle processor:
▪ Advantage: One clock cycle per instruction
▪ Disadvantage: long cycle time
•ET = Insts * CPI * Cycle Time
Execute an
entire instruction
1
T
t pl
The Processor: Datapath & Control
• We’re ready to look at an implementation of MIPS simplified to contain only:
– memory-reference instructions: lw, sw
– arithmetic-logical instructions: add, sub, and, or, slt
– control flow instructions: beq
• Generic Implementation:
– use the program counter (PC) to supply instruction address
– get the instruction from memory
– read registers
– use the instruction to decide exactly what to do
If
What signals accomplish what?
sign bit (adder output from bit 31)
Binvert Cin Oper
ADD
SUB
AND
OR
SLT
BEQ
Let’s look beyond
just Execute now.
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
i
CSE 141 CC BY-NC-ND Pat Pannuto – Many slides adapted from Dean Tullsen 9
Our previous view of a computer had no
organization
• From Part I…
I
fist pose
in sina.to
4t
lean 6ooo
8g W
Which is correct about the ALU and memory in MIPS?
A The ALU always performs an operation before accessing data memory
B The ALU sometimes performs an operation before accessing data memory
C Data memory is always accessed before performing an ALU operation
D Data memory is sometimes accessed before performing an ALU operation
E None of the above
Ala mem in
So what does this tell us?
Mem
IETF
Register Transfer Language (RTL)
• is a mechanism for describing the movement and manipulation of data
between storage elements:
R[3] <- R[5] + R[7] PC <- PC + 4 + R[5] R[rd] <- R[rs] + R[rt] R[rt] <- Mem[R[rs] + immed] add 3 5 7 I add rd.rs rt In Review: The MIPS Instruction Formats • All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type op target address 02631 6 bits 26 bits op rs rt rd shamt funct 061116212631 6 bits 6 bits5 bits5 bits5 bits5 bits op rs rt immediate 016212631 6 bits 16 bits5 bits5 bits 6 5 5 5 6 5 5 16 Ku Su The MIPS Subset • R-type – add rd, rs, rt – sub, and, or, slt • LOAD and STORE – lw rt, rs, imm16 – sw rt, rs, imm16 • BRANCH: – beq rs, rt, imm16 op rs rt rd shamt funct 061116212631 6 bits 6 bits5 bits5 bits5 bits5 bits op rs rt immediate 016212631 6 bits 16 bits5 bits5 bits op rs rt displacement 016212631 6 bits 16 bits5 bits5 bits PC = PC+4 R[rd] = R[rs] OP R[rt] PC = PC+4 R[rt] = Mem[R[rs] + SE(imm)] OR Mem[R[rs] + SE(imm)] = R[rt] ZERO = (R[rs] – R[rt] == 0) if(ZERO) PC = PC + 4+ (SE(Imm)<<2) Else PC = PC+4 EsI l Storage elements • RTL describes data movement between storage elements, but we don’t actually have our data elements yet. • So… Storage Element: Register • Register – Similar to the D Flip Flop except ▪ N-bit input and output ▪ Write Enable input – Write Enable: ▪ 0: Data Out will not change ▪ 1: Data Out will become Data In (on the clock edge) Clk Data In Write Enable N N Data Out I Which of these describes our register file? A Two 32-bit outputs, 3 5-bit inputs, clk input, 1-bit control input B Two 32-bit outputs, 3 32-bit inputs, clk input, 1-bit control input C Two 32-bit outputs, 3 5-bit inputs, 1 32-bit input, clk input, 1-bit control input D Two 32-bit outputs, 2 32-bit inputs, 1 32-bit input, clk input, 1-bit control input E None of the above o o I Let’s try to make a Register File add 11 82 13 fit E suit It 42 32 bit int yay writeadd II writedata i Register File Clk Write Data RegWrite 32 32 Read Data 1 32 Read Data 2 32 32-bit Registers 5 5 5 RR1 RR2 WR Memory Clk Write Data MemWrite 32 32 Read Data Address MemRead t Can we layout a high-level design to do all this now? add rd.rs rt IFit Éj 4É 132 a C Can we layout a high-level design to do all this now?adf.rs rt lwrt imm rs amemerm t j Egt tyF t.IT J 132 Can we layout a high-level design to do all this now? Ladd rd.rs rt twrtgimmfrf R memcrf.ITm rs memfR.IEimmKRfrt iii i Eiyizi 132 Can we layout a high-level design to do all this now? SETIA Edmisten twrtsimmfrd kememerm.ge i É IF I i ÉT j.IE Beg us rt Imm Putting it All Together: A Single Cycle Datapath • We have everything except control signals (later) O