程序代写 MCIT 593 - Introduction to Computer Systems

MCIT 593 – Introduction to Computer Systems
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MCIT 593 – Introduction to Computer Systems

A Basic Model of a Computer
(points to current line in our program)
ADD 0, -20, $0
ADD 0, 10, $1
SUB $0, $1, $0
MPY $0, $4, $5
ADD $0, $5, $0
DIV $0, 5, $0
(AKA: register file, data memory)
CLERK (AKA: CPU & ALU)
Instructions
(AKA: control memory)
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MCIT 593 – Introduction to Computer Systems
Mouse Scanner Disk
MEMORY (instructions & data)
Printer LED Disk
PROCESSING UNIT ALU Regs
PC CONTROL UNIT
Basic design of every modern computer
• Although there are alternatives … (believe it or not)
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MCIT 593 – Introduction to Computer Systems
A Basic Implementation of the Von
2n x k-bit Memory
AR1 AR2 AW
23 x 16-bit Memory
“Register File”
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Single Cycle Implementation of the LC4 ISA
MCIT 593 – Introduction to Computer Systems
Arithmetic ArithMux.CTL Ops
0 SEXT(I[4:0])
ALUMux.CTL
Logical 0 Ops
SEXT(I[5:0])
LogicMux.CTL
SEXT(I[4:0])
Comparator
ALL CTL SIGNALS
I[8:6] rsMux.CTL
I[2:0] rtMux.CTL 0
regFile.WE
regInputMux.CTL
Register File
Write Input
Program Memory
Instruction Address PC[15:0]
Instruction 0x07 1
Data Address Data Output
DATA Memory
Data Input
SEXT(I[8:0]) +
SEXT(I[10:0])
NZP Register
NZP Tester
(0x8000 | UIMM8)
I[7:0] I[10:0]
(PC & 0x8000) | (IMM11<<4) 5 LC4-CPU Block Diagram (SINGLE CYCLE!) loop executes in 1 clock cycle Branch Unit An More Advanced Implementation of the Von : LC4 Property of Penn Engineering 6 MCIT 593 - Introduction to Computer Systems AN IMPLEMENTATION OF THE VON NEUMANN MODEL: LC4 Property of Penn Engineering 8 Single Cycle Implementation of the LC4 ISA MCIT 593 - Introduction to Computer Systems Arithmetic ArithMux.CTL Ops 0 SEXT(I[4:0]) ALUMux.CTL Logical 0 Ops SEXT(I[5:0]) LogicMux.CTL SEXT(I[4:0]) Comparator ALL CTL SIGNALS I[8:6] rsMux.CTL I[2:0] rtMux.CTL 0 regFile.WE Instruction 0x07 1 regInputMux.CTL Register File Write Input Program Memory Instruction Address PC[15:0] Data Address Data Output DATA Memory Data Input SEXT(I[8:0]) + SEXT(I[10:0]) NZP Register NZP Tester (0x8000 | UIMM8) I[7:0] I[10:0] (PC & 0x8000) | (IMM11<<4) 5 Branch Unit LC4-CPU Block Diagram An Implementation of the Von : LC4 Property of Penn Engineering 9 Single Cycle Implementation of the LC4 ISA MCIT 593 - Introduction to Computer Systems ArithMux.CTL 0 SEXT(I[4:0]) Arithmetic Ops ALUMux.CTL Logical 0 Ops SEXT(I[5:0]) SEXT(I[4:0]) LogicMux.CTL Comparator Instruction 0x07 1 ALL CTL SIGNALS I[8:6] rsMux.CTL regFile.WE regInputMux.CTL Register File Write Input Instruction Address PC[15:0] Program Memory SEXT(I[10:0]) SEXT(I[8:0]) (0x8000 | UIMM8) I[7:0] I[10:0] (PC & 0x8000) | (IMM11<<4) 5 LC4-CPU Block Diagram (SINGLE CYCLE!) loop executes in 1 clock cycle Branch Unit Data Address Data Output DATA Memory Data Input An Implementation of the Von : LC4 Property of Penn Engineering 10 MCIT 593 - Introduction to Computer Systems BIG Enhancements Over Our Very Basic CPU Replacing Control Memory • In our basic implementation, control memory was limited • It kept getting wider (11-bits, 15-bits, etc!), each time a new component was added • e.g.: MUX controlling PC, what if we upgraded our ALU to do more than just +/- ??? • There is a better way... Program Memory & Decoder • Instead of storing all of the control signals directly in memory • We store an “instruction” in memory (without control signal data) and add a new device: Decoder • Decoder takes instruction apart and determines the necessary control signals • Fixes instruction length: 16-bits, allows for new control signals without changing instruction length! • Program memory: stores instruction; Decoder: translates instruction into control signals Property of Penn Engineering 11 MCIT 593 - Introduction to Computer Systems BIG Enhancements Over Our Very Basic CPU Upgraded ALU • Now it can ADD/SUB/MULT/DIVIDE, perform logical operations, load constants and much more! • And yes, it can still assist us with comparisons Upgraded Control Unit • More options to control next value of program counter • We rename it the “branch unit”; to indicate that our programs are taking a “branch” / new path Property of Penn Engineering 12 MCIT 593 - Introduction to Computer Systems THE LC4 ISA Property of Penn Engineering 14 MCIT 593 - Introduction to Computer Systems What Is an ISA? Instruction Set Architecture (ISA) • Programmer-visible components & operations • Everything needed to create a program for CPU • Serves as “contract” between programmer & CPU designer • Different implementations of same ISA are “binary compatible” • Ex: Intel/AMD, same x86 ISA, different under the hood Basic Components of any ISA (details are topic of lecture): • How may locations? How many bits per? • Registers • How many? What size? How are they used? • Instruction set • Data types? Opcodes? “Addressing modes”? Property of Penn Engineering 15 MCIT 593 - Introduction to Computer Systems LC4’s ISA: Memory Address Space (how many drawers?) • 16-bit Address Line (so this is a 16-bit ‘machine’) • 216 = 65,535 memory locations (64K) (AKA drawers) Addressability (how many bits per drawer) • 16-bits at each drawer (So a WORD=16 bits on LC4) • Smallest unit of addressable (name-able) memory We partition memory into two main blocks • Program Memory (where we store our instructions) • Data Memory (where we store our data) • Note: in book’s LC3: Instructions & data interleaved arbitrarily Things are different in “real” ISAs • Addressable by byte (8-bits) • Can read/write data in different size chunks (1, 2, 4, 8 bytes) • 64-bit addresses, 264 bytes Property of Penn Engineering 16 MCIT 593 - Introduction to Computer Systems LC4’s ISA: Registers Register File (General Pupose Registers) • Eight Registers: 16-bits wide each • Mnemonically R0–R7 • How many bits to uniquely identify a register? • 8 Registers, so 3 bits Program Counter (PC) Processor Status-Word Register (PSR) • We store the result of the NZP (part 1) in a register! • For one clock cycle • 16-bit PSR • Includes NZP condition codes • Not directly accessible, but used (and affected) by instructions ...all this is the same as LC3 ISA Property of Penn Engineering 17 MCIT 593 - Introduction to Computer Systems LC4’s ISA: Instruction SetàData Types Our memory locations: RegFile, Data Memory are 16-bit • 16-bit 2’s complement integer • 16-bit ASCII characters • 16-bit (555) RGB pixels • No support for floating point! All this is the same as LC3 ISA Property of Penn Engineering 18 MCIT 593 - Introduction to Computer Systems LC4’s ISA: Instruction SetàInstructions 29 Instructions in this ISA 7 Instruction Categories: • Arithmetic Instructions (ADD/SUB/MUL/DIVIDE/ETC) • Logical Instructions (BITWISE AND, OR, ETC) • Shift Instructions • Comparison Instructions • Load/Store Instructions • Loading Constants • Program Control • Branches • TRAP/RTI – Operating System Calls • We’ll now go on a guided tour of instructions from each category • And see how they flow through ISA Property of Penn Engineering 19 MCIT 593 - Introduction to Computer Systems LC4’s ISA: Instruction SetàInstruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fixed length 16-bit instructions Opcode (& sub-opcodes) specify datapath control signals • Decoder ‘looks up’ opcodes and determines control signals 4-bit opcodes: instruction[15:12] • 24=16, but, LC-4 not limited to 16 different instructions • Other bits can be used as sub-opcodes Instructions are same as in LC3 unless noted otherwise Property of Penn Engineering 20 MCIT 593 - Introduction to Computer Systems What’s Inherent in this Architecture? The “Loop” • Fetch instruction at PC • Decode instruction (i.e., convert to control signals) • Execute instruction (read inputs, operate, write output) • Update PC • Rinse, Repeat Critical Requirement • Each iteration of this loop must appear atomic (all or nothing) • Key word from programmer perspective? Atomic • Maintains sanity • Key word from hardware perspective? Appear • Enables hella-cool performance tricks Property of Penn Engineering 21 MCIT 593 - Introduction to Computer Systems TRANSLATING THE ADD INTO ASSEMBLY, MACHINE CODE, AND THEN DECODING IT! Property of Penn Engineering 23 MCIT 593 - Introduction to Computer Systems Example Explanation What is an ADD instruction? Add contents of 2 registers in REG-file together store result in a 3rd register in the REG-file We’ll examine this start to finish on our LC4 machine: 1) Examine instruction format 2) Examine how instruction is decoded 3) Examine how control signals are set around CPU 4) See the steps of Loop and which hardware component implement the various steps Property of Penn Engineering 24 MCIT 593 - Introduction to Computer Systems LC4’s ISA: Instruction: ADD (Register) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Purpose of instruction: Add’s value of two registers in register file, stores result in another register (much like example from last lecture) What CPU does during ADD: 1) regs[DR] = regs[SR1] + regs[SR2] 2) set NZP condition codes 3) PC = PC + 1 Mnemonic for ADD: (We call this Assembly Language) ADDR1,R2,R3 ;COMMENT:R1=R2+R3 Assembly Language to binary translation: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (We call binary translation: machine code) Property of Penn Engineering 25 DR = destination register SR1 = source register 1 SR2 = source register 2 MCIT 593 - Introduction to Computer Systems NOTATION USED IN THE LC4 ISA DIAGRAM Property of Penn Engineering 27 MCIT 593 - Introduction to Computer Systems ISA block diagram uses “BUS” Representation 1512 8 4 0 I = 0 I[14:9] = 101001 We use brackets to denote range: I [15:0] Data [left : right] denotes bit from MSB to LSB May also see angle brackets: I<15:0>
0101 0101 I[2:0] = 101
I “data bus” using this notation as well:
Graphically, you will see a
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MCIT 593 – Introduction to Computer Systems
ADD (REGISTER) INSTRUCTION – STEP 1: FETCH/DECODE
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