代写代考 Laboratory Project: Review MEMORY LAB

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, ART I Objective Design SRAM USING VHDL

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An SRAM retains data bits in its memory as long as power is being supplied to the device. You will create a static random-access memory (SRAM) using D-flip flops. You will be able to store information to different locations within the SRAM and read from it.
You should be familiar with the operation and behavior of D-flip flops before completing the SRAM. As a refresher, D-flip flops will be reviewed.
NOTE: If you already know how to create a D-flip flop, skip the review and move onto creating the Tri-State Buffer.
What is a Flip Flop?
A flip flop is a TWO STATE device (STATE depends on its current input and past sequence of inputs) that changes its STATE upon a change in the clock signal (rising or falling edge of the clock). This means that the device is changing state at a negative or positive edge of the clock signal.
D Flip Flop
A single D Flip Flops stores 1 bit of information upon the rising edge of a clock. In the following image the clock is alternating between 0 and 1 during a certain period of time. We will be evaluating what happens to Q with respect to D when the clock is 1, 0, rising edge or falling edge.
Figure 1: Timing diagram of D-flip flop.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, the clock is 0 and D is 0 Q is whatever it previously was because Q is only affected by a rising edge of the Clock. When D is 1 and the clock is a rising edge Q will become 1. Although D is changing between 0 and 1, Q stays the same because again Q is only affected by D when there is a rising edge. In order to better illustrate figure 1 the following is a truth table explaining the different possible combinations between the clock signal, Input D and the stored value of Q.
Figure 2: Trnsition table for D Flip Flop.
Prepared with the help of Gutierrez, Jeter and Lu, Kelly

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor:
Izidor Gertner
A D-flip flop is essentially a one cell static RAM capable of storing 1 bit of information EXCEPT the SRAM utilizes a tri-state buffer.
The function rising_edge is a clock event detector of a std_logic or std_ulogic signal representative of the clock. It returns true when the signal changes from a low value (¡®0¡¯) to a high value (¡®1¡¯).
NOTE: If you already know how to create a Tri-State buffer, skip its review and move onto creating the SRAM.
Tri-state Logic buffer
You will need a Tri-State buffer for the SRAM. We want to control the flow of data going in and out of the circuit.
A tri-state buffer is a useful device that allows us to control when current passes through the device and when it doesn¡¯t. It returns the value of the input when current is passed into the device: when its selector value is 1. When its selector value is 0, nothing is outputted.
Figure 4: Diagram of Tri-State Buffer. A is the input that is sent to C only when B is ¡®1¡¯. B is this case is the selector.
Prepared with the help of Gutierrez, Jeter and Lu, 3: VHDL code of a D-flip flop

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Figure 5: Truth table of Tri-state Buffer.
Figure 6: VHDL code for Tri-State buffer that you can use.
We will be using a tri-state buffer to read from the SRAM.
Prepared with the help of Gutierrez, Jeter and Lu, Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Now that you understand how to store 1-bit of information, extend it to 4 bits.
Figure 7: Diagram of 4×4 SRAM. 4 addressable locations each capable of storing 4 bits of information, a total of 16 static-RAM cells. The output of each column connects to the same output pin without the use of a multiplexer to separate the lines. As long as the tristate buffer cuts off the output of the other cells, the one cell that is on will be the only output that will be connected to the output pin.
The SRAM has several outputs:
¡ñ DataIn[3..0]: This is the input that will be written into the SRAM at a certain address.
¡ñ A[1..0]: This is the address input. This input determines which row of SRAM Cells will
be turned on to write or read data. A standard 2-to-4 decoder is used to decode the
address input and control the SRAM cells. — YOU WILL MAKE THIS A[3..0]
¡ñ WE: The Write Enable input. This input tells the SRAM to write to the cells when it is
high. If it is low, the chip will not allow any data to be written to any cell.
¡ñ OE: The Output Enable input. When this input is high, it will allow the SRAM to output
the data at the chosen address. Otherwise, the tristate buffer will cut the output of the SRAM off.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, Kelly
¡ñ CS: The Chip Select input. This input, when low, prevents any output from the SRAM and prevents any writing. It turns the SRAM off. Set this high to turn the SRAM on.
In this diagram, there is a 2 to 4 decoder used to select between 4 addresses.
Figure 8: Truth table of 2 to 4 Decoder.
The decoder selects the address to read from or write to. You will need to extend this design to 16 4 bit addresses.
LPM RAM 1-PORT
The final product that you will be using is an LPM RAM 1-PORT. It serves the same purpose as the SRAM you are required design on your own, but it is provided to you by the LPM module. The following are the steps on how to properly create and use it.
To open the menu go to tools and then select Ip catalog.
Figure 9: Dialogue window searching for RAM 1-Port design.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, 10: Make sure that when you are naming the file you select for it to be written in VHDL and not Verilog.
Figure 11: Make sure that you are using these settings when creating the RAM 1-Port, 4 bits wide, using 16 words, just like in the SRAM you are designing.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, Kelly
Figure 12: Do not change anything on the next screen just press next.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, Kelly
Figure 13: Make sure that this dialogue is set to true.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, Kelly
Figure 14: Select leave it blank and then continue by pressing next.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, Kelly
Figure 15: Continue onto the next screen.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, 16: Match these settings and press finish. On the next screen after pressing finish press yes to adding the created file to the current project.
1. Design a 16 x 4 SRAM. The output of this SRAM will be connected to a 4 to 7 decoder that outputs to a seven segment display. Input to the SRAM using 4 switches and a signal to write to memory.
2. Do the same using the LPM RAM 1 PORT.
3. Write a report and film a 1 minute video.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, ART II Objective is to Design a digital circuit to write data to a memory ¡°CHIP¡± on the board, using switches on the board to input addresses and integer data. Therafter, please display integer data stored in memory using 7 segment
In this PART II you will be writing data, at a specified address, to a separate memory ¡°chip¡± Synchronous Static Ram (SSRAM) on the DE2 board, thereafter you will have to display data at the specified address using seven segment display.
To get more information about SSRAM, please refer DE2 board users guide and reference manual.
We summarize here the description of SSRAM on the DE2 board.
The FPGA boards come with memory. In the DE2-115, there are 220 address locations represented by an array of 20 bits: SRAM_ADDR[19..0]. Each address can hold up to 16 bits of

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, Kelly
data that can be accessed via its own Pin. The user manual contains a chart listing the pins of the addresses in the form of an array, with the name SRAM_ADDR[19..0] while the data that can be stored at each address is of the form SRAM_DQ[15..0].
NOTE: In VHDL, the type for the data, SRAM_DQ, is inout instead of just in or out because it can be read from and written to on the FPGA board.
Among other variables that will be required to write to the board, the following will have to be initialized to 0 in order to read and write to the SRAM on the FPGA board:
SRAM_CE_N –Chip Select SRAM_OE_N –Output enable SRAM_UB_N –Sram higher byte strobe SRAM_LB_N –Sram lower byte strobe
– Initialize the variables above, to ¡®0¡¯ in your VHDL code, BUT they are still required to be
assigned to their respective pins on the FPGA board. You will need to set them to ¡®0¡¯ because that is how they will be interpreted as TRUE and grants access to the FPGA boards SRAM.
– Make sure that SRAM_ADDR, SRAM_CE_N, SRAM_OE_N, SRA,_UB_N, SRAM_LB_N, SRAM_LB_N are out signals.
For example on the DE2-115 Board the pins are:
We will be using the SRAM_WE_N (Write enable) to write to a specified address data segment.

Laboratory Project: Review MEMORY LAB
DUE Date: March 14, 2022
Instructor: Professor Izidor Gertner
Prepared with the help of Gutierrez, Jeter and Lu, OUR TASK:
1. Create a circuit using VHDL (QUARTUS< MODELSIM) that will allow you to read and write to 8 addresses, each 8 bits wide, within the board¡¯s memory. USE switches on the board to input addresses and integer data. a. You will be accessing SRAM_ADDR[7..0]. This means that there are 28 different addresses but you will only be writing to 8. Set SRAM_ADDR[19..8], to 0 in your VHDL code. However, you MUST still assign a pin to each SRAM_ADDR. b. Use switches 0-7 to input data into SRAM_DQ[7..0]. Set the values in SRAM_DQ[15...8] to 0 in your VHDL code since you will not be using them. c. You have to verify whether the information will be stored to SRAM_DQ when SRAM_WE_N is 1, 0, rising edge or falling edge. 2. In your simulation and on the DE2 Board, store a different value in 8 different addresses and read from them. Display the values, in hexadecimal, within the SRAM_DQ using 7 segment displays. 3. Write a report and create a 1 min demonstration video. Your circuit will resemble the image below: Laboratory Project: Review MEMORY LAB DUE Date: March 14, 2022 Instructor: Professor Izidor Gertner Prepared with the help of Gutierrez, Jeter and Lu, : Block diagram for Synchronous Static Ram Laboratory Project: Review MEMORY LAB DUE Date: March 14, 2022 Instructor: Professor Izidor Gertner Prepared with the help of Gutierrez, Jeter and Lu, of SRAM design. Your job is to fill in the blanks and make sure to correctly output the SRAM_DQ[15..0] using 7segment displays in Hexadecimal format and on the LED Lights. Laboratory Project: Review MEMORY LAB DUE Date: March 14, 2022 Instructor: Professor Izidor Gertner Prepared with the help of Gutierrez, Jeter and Lu, ISPLAY ON DE2 BOARD: In this image, although SRAM_ADDR and SRAM_DQ are assigned to the correct pins the input data for SRAM_DQ[7..0] is input using the first 8 switches, is shown using first 8 led lights and in the first 2 seven segment displays. In this case we are storing 0000000000001111 into the address 000000000000111111111111. For the DE2-115 Board the pin assignments that will be used are as follows: Laboratory Project: Review MEMORY LAB DUE Date: March 14, 2022 Instructor: Professor Izidor Gertner Prepared with the help of Gutierrez, Jeter and Lu, Kelly 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com