Reconfigurable computing
Digital Design
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Assignment 1
Digital Design Assessment
20 credit module
Assessment
25% Coursework assignment 1 (due 21st April)
25% Coursework assignment 2 (due 9th May)
50% May/June exam
Assignment part 1
Use VHDL to create a simple combination lock
Enter numbers on slider switches
Use push buttons for control
7-segment display
Programming connection to PC
Assignment part 2
Improve the user interface
Display numbers entered by user
Display code “Err” or “OK” in response to code sequence
7-segment display
Programming connection to PC
User can change passcode (after entering correct passcode)
User who has forgotten passcode is prompted to enter memorable information (birthday) and can then change passcode
Assignment part 3
Assignment part 4
Never enter the full pass code in a single session
Systems prompts for two randomly chosen digits in code sequence
User entered required digit from code
Assessment
Demonstrate design in lab
Write report
Introduction
Design ideas and organization
Simulation results
Synthesis results
Conclusion
Provide complete copies of VHDL source code
Lab demo (week 1, summer) 20%
Style, logical structure, presentation 10%
Analysis and design of system 10%
Originality and creativity 10%
Something I didn’t ask for, but makes the system more useful
Technical achievement 50%
How complete your solution is
How well tested and verified it is
Quality of your code
(Commenting, structure, ease of maintenance and modification)
Getting Started
Lab session 4 will introduce the first stage of this assignment
Design Constraint Files *.XDC
An XDC file connects the ports of your VHDL to the pins on the FPGA that are physically connected to particular resources (switches, buttons, LEDs, clocks, …)
Design Constraint Files *.XDC
Every signal in your VHDL top level design source must have a counterpart in the XDC
Names must match (uppercase/lowercase is significant)
Design Constraint Files *.XDC
Every signal in your VHDL top level design source must have a counterpart in the XDC
Names must match (uppercase/lowercase is significant)
Any of the pins on your FPGA That have not been connected in your design should be commented out with a #
Detecting Button Presses
A pressed button will be sampled every 10 ns
Say you enter the number 5 and press the button
Unless you are careful, the device will respond as if you had entered 5,5,5,5,…
To make it respond only once to a single button press, you will need to detect that the button is now 1 and in the last clock cycle it was 0
Detecting Button Presses
To make it respond only once to a single button press, you will need to detect that the button is now 1 and in the last clock cycle it was 0
process(clock)
if rising_edge(clock) then
button_last <= BTNL;
if BTNL=‘1’ and button_last=‘0’ then
end process;
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