2021 COMP3222 Lab 11 Requirements, Marking Guide and Additional Notes
There are 7 marks in total available for this lab.
To assist with your completion of the lab, a project archive containing VHDL file stubs for Part II and a draft
simulation waveform file have been provided in the Lab 11 section of the course website. To help
streamline our testing of your solution, please don’t edit the ENTITY description when completing
your solution to Part II.
Part I (1 mark)
This part essentially asks you to implement the bit counter (popcount operation) discussed in lectures (see
L08/S40-S47). Note, however, that in contrast to the lecture implementation, the circuit you are to implement
needs to load the input word A in state S1 while s is not asserted. Implement the circuit as suggested in the
lab exercise sheet. Use a manually controlled clock signal to test your circuit on the board and switch to the
50MHz clock when the design works as desired.
Part II (5 marks – 3 marks for your paper-based design, 1 mark for describing the circuit in VHDL, 1 mark for
your simulation). You must submit your paper-based design to obtain any marks for Part II.
Before you start coding this part of the lab, you are required to neatly and professionally:
• List the pseudocode for your binary search algorithm,
• Sketch the ASM chart for your design,
• Sketch the data path for your design, label all signals including all internal wires and indicate the
bitwidth of signals that are wider than a single bit,
• Refine your ASM chart with the names of the signals that are to be asserted/tested during each
state or state transition, and
• Sketch a timing diagram of your design assuming that the input value is found at the second
address that the search explores. The diagram should include the name of the current state and the
address and data of the RAM component. Remember that it takes 2 clock cycles to read from
memory using the default settings.
Implement your design but DO NOT map it to the board – that is, archive it after you are happy with
your simulation. In other words, perform steps 1, 2, 3 and 5 of the lab instructions for Part II BUT NOT
STEP 4 – your submission for this part is ready for archiving when you have completed the simulation.
● HINT: Your binary search will require a division by 2, but there is no division operator in VHDL!
Use a logical right shift to perform the same arithmetic.
● WARNING: Take care with the search bounds especially at the conclusion of each search!
● Include a ‘DONE’ signal in your design that behaves in the same way as in Part I.
● Prepare a simulation that sequentially searches for the values 0 to 64. The odd values from 1 to 63
should be stored in RAM.
● Use the ‘clock’ signal setup to configure the ‘clock’ and ‘start (s)’ signals
● Use the ‘counter’ signal setup to configure the input
Note that a project archive containing skeleton VHDL code, including the interface of the design, a
preconfigured and pre-initialized 1-port RAM module, and a simulation waveform file using the provided
interface has been made available for your use. The simulation waveform assumes your design uses 6 clock
cycles or less to explore each search address.
Further note for advanced students (not marked): while we are not marking off the circuit operating on
the board, you may like to challenge yourself to minimize the number of clock cycles needed to explore each
search address. It is possible to compute a search address and to ascertain the value stored at that address
every two clock cycles. Getting to one clock cycle would be brilliant! Check the impact on Fmax as you
reduce the number of clock cycles used.
1 mark
1 mark
1 mark
Coding style (1 mark)
Apart from correctness, the guiding principle for code style in COMP3222 is understandability and
maintainability. Up to ONE mark will be awarded for your coding style on both assessable parts of the lab.
Points to be taken into account include:
• Adherence to the lab specifications
• Alignment between your paper designs and your code
• Appropriate decomposition of a design into sub-components
• Correct VHDL use, including appropriate use of behavioural statements and component instantiation
• Use of meaningful names for entities, architectures, signals and labels
• Proper indentation
Submission
1. Create a project archive of your implementation of Part I and a project archive of your VHDL code
and simulation of Part II. Use meaningful names to distinguish between the two archives e.g. L11P1
and L11P2. Include your surname, student number, lab and part number in the archive name e.g.
Diessel-3002283-L11P1.qar
2. Create a PDF or JPEG file of the paper designs for Part II. Use the same naming convention as
above, but append -design.pdf or -design.jpg e.g. Diessel-3002283-L11P2-design.pdf
3. Create a zip file including the above 3 files and submit it using the Make Submission tab on the Lab
11 additional guidelines and questions link of the course website. Submissions are due at 23:59 on
22 November.