s3
Review on
Synthesizable VHDL
Steve Wilton
University of British Columbia
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Introduction
For the most part, in this course, you are writing a fairly small
VHDL Description
For larger designs, if you aren’t *really* careful,
it is likely that when you try to compile
your code to hardware, it won’t work!
Why?
I’ll tell you in this slide set, and also talk
about how to make sure it does work.
Why is this so important?
Because, it will save you tons of debugging time in the lab if you
understand it.
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Recall: What is VHDL?
VHDLs serves two roles:
• Synthesis – Describe hardware that you ultimately want to create
• Simulation – Describe hardware for simulation, and describe tests
Subset of VHDL that can be synthesized is called synthesizable VHDL
– Many legal VHDL constructs can not be synthesized
Design Files
(VHDL)
Simulation Results
Bitstream to
Program FPGA
Testbench
(VHDL)
Modelsim Quartus II
Synthesizable VHDL
Any legal VHDL
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Not all VHDL Code can be synthesized by current tools.
– This isn’t limited to our tools
Synthesizable VHDL is a subset of VHDL that can be synthesized
by current tools.
If you write VHDL that is not synthesizable:
– Tools will not be able to create hardware
• Sometimes it will try, but end up with something that is “not quite right”
• Sometimes it gives an error message, sometimes not!
Moral: if you are going to synthesize, always write Synthesizable VHDL!
“Synthesizable” VHDL
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odiessel
Rectangle
Synthesizable Language Constructs
• Entities/Architectures
• Signals
• Concurrent Signal Assignments
• Component Instantiations
• Processes
– If/else Conditional Statement
– Case Statement
These are generally synthesizable …
To be Synthesizable, there needs to be a way to determine an
equivalent gate-level implementation of the construct
For all of the constructs above, there is a straight-forward “recipe” to
determine the gate-level implementation …
…except for the PROCESS
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process(….)
begin
….
end process
process(….)
begin
….
end process
process(….)
begin
….
end process
Y <= …
X <= …
Subcircuit
Subcircuit
Subcircuit
Subcircuit
Subcircuit
A modern synthesis tool:
- Extracts processes and concurrent assignments from the code
- Converts each process and concurrent assignment
to a piece of hardware
Each process
or concurrent
assignment
is treated
separately.
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Synthesis of VHDL Processes
We use the VHDL Process to model the behaviour of a block of hardware.
The synthesis tool then tries its best to find a hardware implementation
that matches this behaviour.
IN0
IN1
OUT0
OUT0
Behavioural
(algorithmic-like description)
if ( rising_edge (CLK) ) then
if ( RESET = ‘1’ ) then
OUT0 <= ‘0’;
...
elsif ( EN = ‘1’) then
case IN0 is
when ...
...
end case;
end if;
end if;
PROCESS
It’s possible to write a process in such a way,
that it becomes non-synthesizable
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Three Coding Patterns
Synthesis tools use PATTERN MATCHING on each process to
determine its hardware implementation
Three patterns that ALL synthesis tools can understand
1. Purely Combinational
2. Sequential
3. Sequential with asynchronous reset
ANY PROCESS THAT YOU WRITE MUST
USE ONE OF THESE THREE PATTERNS
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Pattern 1. Purely Combinational
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1. Purely Combinational
Process outputs are a function of the current input values
Rule 1A:
• Every input to the process must be in the sensitivity list (or in VHDL
2008, the sensitivity list must only contain the keyword all)
Rule 1B:
• Every output must be assigned a value for every possible
combination of inputs.
• In other words, every output must be assigned a value for every
possible path through the process’ description
PROC: process (A, B, SEL)
begin
if (SEL = ‘1’) then
C <= A;
else
C <= B;
end if;
end process;
A
B
PROC
C
1
0
SEL
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1A. Sensitivity List Rule
Rule 1A:
• Every input to the process must be in the sensitivity list
If you break this rule, you are saying…
… “If an event occurs on the input signal, do not immediately update
the output”
-- Note: SEL is missing
-- from sensitivity list
PROC: process (A, B)
begin
if (SEL = ‘1’) then
C <= A;
else
C <= B;
end if;
end process;
From Quartus:
Warning (10492): VHDL Process
Statement warning at testtest.vhd(15):
signal "SEL" is read inside the Process
Statement but isn't in the Process
Statement's sensitivity list
Quartus is actually smart enough in this case, but don’t rely on this in
general. And your simulations will definitely be wrong.Page 11
Did not include C in sensitivity list
for a combinational process
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1B. Output Assignment
Rule 1B:
• Every output must be assigned a value for every possible
combination of input values.
• In other words, every output must be assigned a value for every
possible path through the process’ description
If you break this rule, you are saying…
… “For the combination of input values where we don’t assign a value
to the output, the output should remember its old value.”
à Memory is implied à Sequential
PROC: process (A, B, SEL)
begin
if (SEL = ‘1’) then
C <= A;
end if;
end process;
From Quartus:
Warning (10631): VHDL Process
Statement warning at testtest.vhd(13):
inferring latch(es) for signal or variable "C",
which holds its previous value in one or
more paths through the process
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If Sel is not 0, Z is not
assigned a value.
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1B. Output Assignment
Rule 1B:
• Every output must be assigned a value for every possible
combination of input values.
• In other words, every output must be assigned a value for every
possible path through the process’ description
The following works though:
PROC: process (A, B, SEL)
begin
C <= B;
if (SEL = ‘1’) then
C <= A;
end if;
end process;
A
B
PROC
C
1
0
SEL
Make sure you understand why!
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CASE Statement
If you don’t handle all choices in the CASE statement it actually gives
you an error. So you won’t accidentally get the wrong circuit.
-- Assume SEL is 2-bits
PROC: process (A, B, C, SEL)
begin
-- Note: Missing “11”
case SEL is
when “00” => F <= A;
when “01” => F <= B;
when “10” => F <= C;
end process;
From Quartus:
Error (10313): VHDL Case
Statement error at testtest.vhd(16):
Case Statement choices must cover
all possible values of expression
BEST PRACTICE: Use when others to catch all other cases
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Summary: 1. Purely Combinational
Process outputs are a function of the current input values
Rule 1A:
• Every input to the process must be in the sensitivity list or use
keyword all in VHDL 2008
Rule 1B:
• Every output must be assigned a value for every possible
combination of inputs.
• In other words, every output must be assigned a value for every
possible path through the process’ description
PROC: process (A, B, SEL)
begin
if (SEL = ‘1’) then
C <= A;
else
C <= B;
end if;
end process;
A
B
PROC
C
1
0
SEL
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Pattern 2. Sequential
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2. Sequential
Each output changes ONLY on the rising or falling edge of a single clock
Rule 2A:
• Only the clock should be in the sensitivity list
Rule 2B:
• Only signals that change on the same edge of the same clock
should be part of the same process
process (CLK)
begin
if (rising_edge(CLK)) then
end if;
end process;
Sequential Circuit with Synchronous Reset
Falls Under This Category Page 19
Included D in sensitivity list for
a flip-flop
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Flip Flop Reset Signals
A flip-flop can have either a synchronous or asynchronous reset
Asynchronous Reset: When the reset signal is high, the flip-flop is
reset (forced to ‘0’) immediately, regardless of the clock.
Synchronous Reset: On a rising clock edge, if the reset signal is high,
The flip-flop is reset (forced to ‘0’).
The difference
Synchronous reset à flip-flop only resets on a rising clock edge
Asynchronous reset à flip-flop resets immediately
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Recall rule for Pattern 2: Each output changes ONLY on the rising or
falling edge of a single clock
Do either of these match this pattern?
Asynchronous Reset: When the reset signal is high, the flip-flop is
reset (forced to ‘0’) immediately, regardless of the clock.
Synchronous Reset: On a rising clock edge, if the reset signal is high,
The flip-flop is reset (forced to ‘0’).
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Describing DFF with Synchronous Reset
Synchronous Reset: On a rising clock edge, if the reset signal is high,
The flip-flop is reset (forced to ‘0’).
architecture ARCH of DFF is
begin
process (CLK)
begin
if (rising_edge(CLK)) then
if (RESET = ‘1’) then
Q <= ‘0’;
else
Q <= D;
end if;
end if;
end process;
end architecture;
Reset behaviour described inside rising clock edge case
Reset Case {
Normal Operation}
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DFF With Synchronous Reset
Behaviour is equivalent to:
0
D
Q
1
0
Reset
D Q
CLK
D Q
Reset
D Q
CLK
RST
But there are better transistor level implementations of such functionality and
we just assume that it’s possible to create such a flip flop with synchronous
reset input
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Asynchronous Reset: When the reset signal is high, the flip-flop is
reset (forced to ‘0’) immediately, regardless of the clock.
Synchronous Reset: On a rising clock edge, if the reset signal is high,
The flip-flop is reset (forced to ‘0’).
✔ Pattern 2
?
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Pattern 3. Sequential with
Asynchronous Reset
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3. Sequential with Asynchronous Reset
Reset occurs immediately
Rule 3A:
• Sensitivity list includes clock and reset
process (CLK, RESET)
begin
if (RESET = ‘1’) then
elsif (rising_edge(CLK)) then
end if;
end process;
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3. Sequential with Asynchronous Reset
Rule 3B:
• Assignments in the reset part can only reference constants or literals
process (CLK, RESET)
begin
if ( RESET = ‘1’ ) then
A <= ‘0’; -- YES
B <= ANOTHER_SIG; -- NO
elsif ( rising_edge(CLK) ) then
...
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Describing DFF with Asynchronous Reset
Asynchronous Reset: When the reset signal is high, the flip-flop is
reset (forced to ‘0’) immediately, regardless of the clock.
architecture ARCH of DFF is
begin
process (CLK, RESET)
begin
if (RESET = ‘1’) then
Q <= ‘0’;
elsif (rising_edge(CLK)) then
Q <= D;
end if;
end process;
end architecture;
Reset behaviour described before rising clock edge case
Reset Case {
Normal Operation}
RESET now in
sensitivity list}
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Final Rule (the most important rule of all):
If you want to synthesize your circuit, every process must
fall exactly into one of these categories. Every process.
Every single one. No exceptions.
If one of your processes doesn’t, you need to break it up
into blocks, where each block does fit into one of these
categories.
(note: I am being a little bit conservative here… some synthesizers
will handle a few patterns not described here. But don’t count
on it).
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Summary: Synthesizable Processes
Make sure all of your processes fall under
one of these three patterns
If one of them doesn’t then break it into multiple processes that do!
I’m being conservative. Some synthesis tools can handle
more complex patterns. But don’t count on it
TIP: Anytime you write a process, ask your self
“Does this process fall under one of these three patterns?”
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