COMP3222/9222 Digital Circuits & Systems
10. Course Wrap-up
Outline
• Learning objectives
• Topic list
• Assessment
• Exams
• Reminders
• myExperience
20T3 COMP3222/9222 Course Wrap-up L10/S2
Learning objectives
• How to design and analyze digital logic circuits
– Boolean algebra, logic minimization, combinational logic components,
sequential circuits, simple systems
– Boolean logic theorems, Karnaugh maps, Shannon’s theorem, Moore &
Mealy FSMs, ASMs
– cost, speed, power, understandability, maintainability
– fine-grained parallelism
– implementation technologies
• How to specify/simulate/synthesize/implement designs
– VHDL hardware description language
– simulation techniques to verify the correct working of our designs
– logic compilers to synthesize the hardware blocks of our designs
– implementing designs using programmable hardware
– testing hardware implementations of circuits
20T3 COMP3222/9222 Course Wrap-up L10/S3
Topic list – Digital circuits
• Boolean algebra
• SOP & POS form
• NAND/NOR-only forms
• Implementation technologies
• Logic/circuit minimization; circuit
cost
• Factoring & functional
decomposition
• Analyzing circuits
• Number representation
• Arithmetic circuits; circuit speed
• Combinational circuit blocks
• Implementing combinational
functions using MUXes,
DECoders & LUTs
• Latches & flip-flops
• Counters, registers
• Timing properties & analysis of
digital circuits
• Synchronous sequential circuit
design involving FSMs, state
transition diagrams, state tables,
state minimization, state
assignment etc.
• Moore & Mealy models
• Algorithmic state machines
• Digital system design; datapath
and control path design
• Hardware handshakes
20T3 COMP3222/9222 Course Wrap-up L10/S4
Topic list – VHDL
• Entities & architectures
• Concurrent/sequential statement
types; differences with sequential
programming language semantics
• Describing combinational &
sequential circuit components
• Structural vs behavioural
description
• Use of sub-components in
structural descriptions
• Packages
• Understanding the three types of
reliably synthesizable processes
• Specifying FSMs
• Specifying datapaths
• Describing complete digital
systems comprising both data and
control paths
• Experience with a CAD tool for
synthesizing & simulating designs
• Experience implementing and
testing circuits on an FPGA
prototyping board
20T3 COMP3222/9222 Course Wrap-up L10/S5
COMP3222/9222 Assessment details
• Assessment:
– Lab exercises: 40%
– 4 fortnightly quizzes: 20%
– FINAL ONLINE THEORY & PRACTICAL EXAMS:
– 2:00 – 6:30pm, MONDAY 30 NOVEMBER
• 1 hr Final Theory Test: 15%
• 2 hr Final Practical Test: 25% you must score >40% in this part to
pass the course
20T3 COMP3222/9222 Course Wrap-up L10/S6
COMP3222 Exams
Final Theory exam
• Available on Moodle from 2:00 – 3:30 pm on Monday 30 Nov
• Time allowed: 80 minutes, including approximately 10 minutes
reading time and 10 minutes to upload files with minor network
glitches – commence ASAP after 2:00 pm to get full 80 minutes
• Suggest you be logged into Moodle by 1:55 pm; refresh your
session after 2:00 pm to commence the exam
• The exam comprises 3 long answer questions; split into multiple
subquestions; some involve uploading scanned copies of written
work
• Please try the Practice Theory exam (from the Exams menu item
on the course website) to familiarize yourself with the rules, the style
of questions, and file uploads using Moodle
Course Wrap-up L10/S720T3 COMP3222/9222
COMP3222 Exams
Final Practical exam
• Available on WebCMS from 4:00 – 6:30 pm on Monday 30 Nov
• Time allowed: 140 minutes, including approximately 10 minutes
reading time and 10 minutes to upload files with minor network
glitches – commence ASAP after 4:00 pm to get full 140 minutes
• Suggest you be logged into WebCMS by 3:55 pm; refresh your
session after 4:00 pm to commence the exam
• The exam comprises 4 long answer questions; three involve
uploading scanned copies of written work; the fourth involves
submitting a Quartus project archive of your implementation
• Please try the Practice Practical exam (from the Exams menu item
on the course website) to familiarize yourself with the rules, the style
of questions, and file submissions using WebCMS
Course Wrap-up L10/S820T3 COMP3222/9222
Exam details
READ THE INSTRUCTIONS!!
Theory Part
• Covers all lecture material
• Will comprise design questions
• ANY OFFLINE MATERIALS ALLOWED INCLUDING MATERIAL ON THE
COURSE WEBSITE
Practical Part
• Will require you to design and implement a small digital system
• ALLOWED TO USE ANY OFFLINE REFERENCE MATERIALS INCLUDING
MATERIALS ON THE COURSE WEBSITE AND LAB FILES
• ASKING FOR HELP OF ANYONE OR USING THE INTERNET TO ASSIST
OR COPYING ANY EXAM MATERIAL IS NOT PERMITTED
• Contact me by phone, email or Teams if you have any questions or difficulties
• Take screen images, obtain reports of network outages etc.
• Lodge request for special consideration and submit evidence if impacted
20T3 COMP3222/9222 Course Wrap-up L10/S9
Reminders
• Today is the last lecture
• LAB11 is due next Monday
• Stay tuned for an announcement on returning your lab kit
– Failure to return the lab kit when requested may result in delayed results or a
service block being imposed on your record
20T3 COMP3222/9222 Course Wrap-up L10/S10
Please fill in the myExperience Course Survey
Your opinions are important to us
– Course surveys help! We do take notice and make changes to improve
quality
So PLEASE take 10 mins NOW and tell us what you thought of the course
Thanks! & Good Luck!
20T3 COMP3222/9222 Course Wrap-up L10/S11
Secondary details go here
Tell us about your experience
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education at UNSW.
Click the link in Moodle