2021 COMP3222 Lab 9 Requirements, Marking Guide and Additional Notes
Lab 9 has two parts. You are required to complete and submit solutions for the simulation and board
implementation of Part I. Part II is optional.
Completing Part I successfully will score up to 4 marks contributing to the lab component of your assessment
– up to one mark will be awarded for your paper design, comprising a Mealy state diagram and multiplexor
truth table; up to one mark will be awarded for a project archive that includes a simulation that replicates the
waveform provided in Figure 3; up to one mark will be awarded for a second project archive that maps the
processor to your DE board and functions correctly on the board; and up to one mark will be awarded for
good coding style. It is a requirement to be awarded any marks for Part I that you submit your paper
design.
OPTIONAL: If you complete and submit correct solutions to Parts I & II of the lab, you will be awarded ONE
bonus mark in the course.
To assist with your completion of the lab, a project archive containing VHDL file stubs for Part I have been
provided in the Lab 9 section of the course website. To help streamline our testing of your solution,
please don’t edit the ENTITY description when completing your simulation of the processor.
Part I
In this part, you are provided with the block diagram of a processor (Figure 1) and a soft copy of skeleton
code (Figure 2a-2c) within the L9P1sim project archive. You are expected to complete the design and
implementation of the processor.
1. Use the skeleton code to identify the control unit FSM and produce a Mealy state diagram prior to
coding. Your diagram must be included in your lab submission.
2. Produce a truth table for the Multiplexers unit prior to coding. Your truth table must be included in
your lab submission.
3. Implement the adder/subtractor unit.
4. Instantiate all necessary registers and interconnect them.
5. Produce a simulation waveform as depicted in Figure 3 to validate your design prior to mapping the
processor to the DE1 Starter Board. You must archive your project when you complete this step and
before mapping the processor to your DE board. Include this archive in your lab submission.
6. Creating a new (second) project called L9P1brd and map the processor from steps 1-5 above to
your DE board as specified in steps 4-6 of the Laboratory 9 Exercise sheet for Part I. Name your top-
level design entity that refers to the DE board switches, keys and LEDs L9P1brd. Instantiate your
processor within this design entity. Test your design on the board using the inputs given in the
simulation of Figure 3 and ensure that it works correctly. Archive this project and include a copy of
the archive in your lab submission.
IMPORTANT Note 1: We will not mark your submission without your paper-based designs for the FSM’s
state diagram and Multiplexers’ truth table.
Note 2: You must adhere to the block diagram given in Figure 1 and implement the circuit as illustrated.
Note 3: For your functional simulation only use the signals and waveforms provided in Figure 3. The
necessary signals can be found in the node finder window by listing “Design Entry (all names)” and selecting
the Combinational Groups corresponding to the Q outputs of the desired registers.
Note 4: In order to display the state Tstep_Q you may need to select an alternative to the default (and
recommended) ModelSim simulator. This is achieved by selecting the Simulation → Options menu item from
the top of the waveform viewer window and selecting the Quartus II Simulator rather than the ModelSim
Simulator.
OPTIONAL Part II
Note 1: Implement the circuit exactly as shown in Figure 4.
Note 2: Follow the MIF file format as described on the Intel Quartus Memory Initialization File (.mif) Definition
page.
(https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/reference/glossary/def_mif.htm)
Note 3: Demonstrate your solution by encoding precisely those instructions you used to simulate the
processor in Part I, step 5 above, in your MIF file and executing these.
Create a project archive of your working solution using the name L9P2.
Coding style
Apart from correctness, the guiding principle for code style in COMP3222 is understandability and
maintainability. Up to ONE mark will be awarded for your coding style on all three assessable parts of the
lab. Points to be taken into account include:
• Adherence to the lab specifications
• Alignment between your paper designs and your code
• Appropriate decomposition of a design into sub-components
• Correct VHDL use, including appropriate use of behavioural statements and component instantiation
• Use of meaningful names for entities, architectures, signals and labels
• Proper indentation
Submission
1. Create a Project → Archive for both the simulation and the implementation of Part I as described in
Steps 5 and 6 above. Use meaningful names to distinguish between the two archives e.g. L9P1sim
and L9P1brd. Include your surname, student number, lab and part number in the archive name e.g.
Diessel-3002283-L9P1sim.qar
2. Create a PDF or JPEG file of the paper designs for Part I. Use the same naming convention as
above, but append -design.pdf or -design.jpg e.g. Diessel-3002283-L9P1-design.pdf
3. If you are submitting a solution for Part II, please use the same naming convention for your archive
of this part e.g. Diessel-3002283-L9P2.qar
4. Create a zip file including the above 3 (or optionally 4) files and submit it using the Make Submission
tab on the Lab 9 additional guidelines and questions link of the course website. Submissions are
due at 23:59 on 8 November.
https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/reference/glossary/def_mif.htm