COMP3222/9222 Digital Circuits & Systems
9. Implementation Technology
Objectives
• Learn about integrated circuit implementation technologies
• Understand the structure and operation of CMOS logic gates
• Know about the variety of digital implementation technologies and
their application
• Review the structure of field-programmable gate arrays and other
programmable logic devices
20T3 COMP3222/9222 Implementation Technology L09/S2
Logic value 1
Undefined
Logic value 0
Voltage
V DD
V 1,min
V 0,max
V SS (Gnd)
Logic values as voltage levels
• Logic variables are
physically represented
using voltage or current
levels
– Use of voltage levels more
common
• Usually, logic 0 is
represented by a low
voltage level and logic 1
by a high V level
– Known as a positive logic
system
B&V3, Figure 3.1
Usually 0V
Usually 1–5V
Usually 60%
of VDD-VSS
Usually 40%
of VDD-VSS
Undefined
Logic
value 1
Logic
value 0
20T3 COMP3222/9222 Implementation Technology L09/S3
Drain Source
x = “low” x = “high”
(a) A simple switch controlled by the input x
V D V S
(b) nMOS transistor
Gate
(c) Simplified symbol for an nMOS transistor
V G
Substrate (Body)
nMOS transistor as a switch
• Logic circuits are built with
transistors operated in cutoff or
saturation modes
• The most popular type of
transistor for implementing a
switch is the metal oxide
semiconductor field-effect
transistor (MOSFET)
– Two types: n-channel or nMOS
and p-channel or pMOS
• In nMOS, the terminal with the
lower voltage level is deemed to
be the source (of electrons)
– When VG is below a so-called
threshold voltage, vt, there is no
connection between the source and
drain – the device is turned off
– When VG > vt, the device is switched
on and VD ≅ VSB&V3, Figure 3.2
20T3 COMP3222/9222 Implementation Technology L09/S4
Gate
x = “high” x = “low”
(a) A switch with the opposite behavior of Figure 3.2 a
V G
V D V S
(b) pMOS transistor
(c) Simplified symbol for a pMOS transistor
V DD
Drain Source
Substrate (Body)
pMOS transistor as a switch
• pMOS transistors have
the opposite behaviour of
nMOS transistors
– Here, the voltage at the
source (of holes) is higher
than at the drain
– The substrate is connected
to VDD (source voltage)
rather than ground
– VG < VB to allow current to flow from source to drain and for VD = VS B&V3, Figure 3.3 20T3 COMP3222/9222 Implementation Technology L09/S5 nMOS operation – cutoff → subthreshold (vGS< vt) 20T3 COMP3222/9222 Implementation Technology Image due to: F. Najmabadi, UCSD See 3222 website for his lecture notes L09/S6 nMOS operation – triode mode (vGS >vt & vDS< vGS–vt) 20T3 COMP3222/9222 Implementation Technology Image due to: F. Najmabadi, UCSD See 3222 website for his lecture notes L09/S7 nMOS operation – pinchoff (vDS → vGS – vt) 20T3 COMP3222/9222 Implementation Technology Image due to: F. Najmabadi, UCSD See 3222 website for his lecture notes L09/S8 nMOS operation – saturation (vDS ≥ vGS – vt) 20T3 COMP3222/9222 Implementation Technology Image due to: F. Najmabadi, UCSD See 3222 website for his lecture notes L09/S9 vDS ≥ vGS – Vt vDS = 0 vDS DrainChannelSource nMOS operation – V-I characteristic 20T3 COMP3222/9222 Implementation Technology Image due to: F. Najmabadi, UCSD See 3222 website for his lecture notes L09/S10 (a) nMOS transistor V G V D V S = 0 V V S = V DD V D V G Closed switch when V G = V DD V D = 0 V Open switch when V G = 0 V V D Open switch when V G = V DD V D V DD Closed switch when V G = 0 V V D = V DD V DD (b) pMOS transistor nMOS and pMOS transistors in logic circuits B&V3, Figure 3.4 When switched on (saturated), the nMOS drain is pulled down to ground When switched on, the pMOS drain is pulled up to VS = VDD 20T3 COMP3222/9222 Implementation Technology L09/S11 (saturated) (cut off) (cut off) (saturated) (b) Simplified circuit diagram V x V f V DD (c) Graphical symbol x f R V x V f R + - (a) Circuit diagram 5 V A NOT gate built using nMOS technology B&V3, Figure 3.5 The resistor limits current flow through the transistor 20T3 COMP3222/9222 Implementation Technology L09/S12 V f V DD (a) Circuit (c) Graphical symbol (b) Truth table f 0 0 1 1 0 1 0 1 1 1 1 0 x 1 x 2 f V x 2 V x 1 x 1 x 2 nMOS realization of a NAND gate B&V3, Figure 3.6 20T3 COMP3222/9222 Implementation Technology L09/S13 nMOS realization of a NOR gate B&V3, Figure 3.7 V x 1 V x 2 V f V DD (a) Circuit (c) Graphical symbols (b) Truth table f 0 0 1 1 0 1 0 1 1 0 0 0 x 1 x 2 f f x 1 x 2 x 1 x 2 20T3 COMP3222/9222 Implementation Technology (c) Graphical symbol L09/S14 (a) Circuit (c) Graphical symbol (b) Truth table f 0 0 1 1 0 1 0 1 0 0 0 1 x 1 x 2 f V f V DD A V x 1 V x 2 x 1 x 2 V DD nMOS realization of an AND gate B&V3, Figure 3.8 20T3 COMP3222/9222 Implementation Technology Constructed from a NAND gate followed by an INVERTER L09/S15 (a) Circuit (c) Graphical symbols (b) Truth table f 0 0 1 1 0 1 0 1 0 1 1 1 x 1 x 2 f f V f V DD V x 2 V x 1 x 1 x 2 x 1 x 2 V DD nMOS realization of an OR gate B&V3, Figure 3.9 20T3 COMP3222/9222 Implementation Technology (c) Graphical symbol L09/S16 V f V DD Pull-down network V x 1 V x n (PDN) Structure of an nMOS circuit • Generalizing the forgoing structures, note that the nMOS transistor network acts to pull the drain to ground • We can derive an equivalent pMOS circuit for each of the previous circuits • We can also combine both nMOS and pMOS networks together in what is known as complementary MOS (CMOS) technology – Involves replacing the pull-up resistor with a pull-up network that complements the structure of the nMOS-based pull-down network – Eliminates the power dissipation in the current-limiting resistor & simplifies fabrication B&V3, Figure 3.10 Pull-down network (PDN) 20T3 COMP3222/9222 Implementation Technology L09/S17 V f V DD Pull-down network Pull-up network V x 1 V x n (PUN) (PDN) Structure of a CMOS circuit • The functions realized by the PUN and PDN are complements of each other – For any valuation of the inputs, either the PDN pulls Vf down to ground or the PUN pulls Vf up to VDD • The PUN & PDN have equal numbers of transistors and are arranged such that the networks are duals of each other – Wherever the PDN has nMOS transistors in series, the PUN has pMOS transistors in parallel and vice versa B&V3, Figure 3.11 Pull-down network (PDN) Pull-up network (PUN) 20T3 COMP3222/9222 Implementation Technology L09/S18 (a) Circuit V f V DD V x (b) Truth table and transistor states on off off on 1 0 0 1 f x T 1 T 2 T 1 T 2 CMOS realization of a NOT gate • Note that ALMOST no current flows in a CMOS inverter when the input is either low or high. • This is true for all CMOS circuits; ALMOST no current flows, and hence ALMOST no power is dissipated under steady state conditions. • However, such leakage current (through the gate) mounts as the transistor feature sizes and threshold voltages (gate voltage at which current just begins to flow) decrease • So called dynamic power or switching power is transitionally dissipated when the gate changes state – the amount dissipated is proportional to the clock frequency and the square of the supply voltage VDD B&V3, Figure 3.12 20T3 COMP3222/9222 Implementation Technology L09/S19 CMOS realization of a NAND gate B&V3, Figure 3.13 (a) Circuit V f V DD (b) Truth table and transistor states on on on off 0 1 0 0 1 1 0 1 off off on off off on f off on 1 1 1 0 off off on on V x 1 V x 2 T 1 T 2 T 3 T 4 x 1 x 2 T 1 T 2 T 3 T 4 • The circuit can be derived from the NAND function f = x1x2 • This expression specifies the conditions for which f = 1; hence it defines the PUN: • From DeMorgan, f = x1x2 = x1 + x2 – Thus f = 1 when either x1 or x2 have the value 0, which means the PUN must have two pMOS transistors connected in parallel • The PDN must implement the complement of f which is f = x1x2 – Since f = 1, and thus f = 0, when both x1 and x2 are 1, the PDN must have two nMOS transistors in series (a) Circuit V f V DD (b) Truth table and transistor states on on on off 0 1 0 0 1 1 0 1 off off on off off on f off on 1 1 1 0 off off on on V x 1 V x 2 T 1 T 2 T 3 T 4 x 1 x 2 T 1 T 2 T 3 T 4 20T3 COMP3222/9222 Implementation Technology L09/S20 (a) C ircuit V f V D D (b) T ruth table and transistor states on on on off 0 1 0 0 1 1 0 1 off off on off off on f off on 1 0 0 0 off off on on V x 1 V x 2 T 1 T 2 T 3 T 4 x 1 x 2 T 1 T 2 T 3 T 4 CMOS realization of a NOR gate B&V3, Figure 3.14 20T3 COMP3222/9222 Implementation Technology (b) Truth table and transistor states L09/S21 V f V DD V x 1 V x 2 V DD CMOS realization of an AND gate B&V3, Figure 3.15 20T3 COMP3222/9222 Implementation Technology Since two more transistors are needed to construct CMOS AND/OR gates, NAND/NOR logic networks are preferred L09/S22 V f V DD V x 1 V x 2 V x 3 The circuit for f = x1 + x2x3 • The PUN is readily derived since all variables appear in complemented form • Use DeMorgan to derive the PDN: f = x1 + x2x3 = x1(x2 + x3) B&V3, Figure 3.16 20T3 COMP3222/9222 Implementation Technology L09/S23 Note voltage levels for the NAND circuit… B&V3, Figure 3.18 (a) Circuit V f V DD (b) Voltage levels L H L L H H L H H H H L V x 1 V x 2 V x 1 V x 2 V f (b) Negative logic truth table and gate symbol 1 1 0 0 1 0 1 0 0 0 0 1 x 1 x 2 f f x 1 x 2 (a) Positive logic truth table and gate symbol f 0 0 1 1 0 1 0 1 1 1 1 0 x 1 x 2 f x 1 x 2 Obtained by assigning logic=1 to voltage=L & logic=0 to voltage=H 20T3 COMP3222/9222 Implementation Technology L09/S24 Tell us about your experience and shape the future of education at UNSW. Click the link in Moodle Please be mindful of the UNSW Student Code of Conduct as you provide feedback. At UNSW we aim to provide a respectful community and ask you to be careful to avoid any language that is sexist, racist or likely to be hurtful. You should feel confident that you can provide both positive and negative feedback but please be considerate in how you communicate. https://student.unsw.edu.au/conduct (a) Dual-inline package (b) Structure of 7404 chip V DD Gnd A 7400-series chip B&V3, Figure 3.21 7400-series packages, a highly successful example of integrated circuit technology introduced in the 1960s, were widely used until the mid-1980s. Because of their low logic capacity, these standard chips are seldom used today 20T3 COMP3222/9222 Implementation Technology L09/S26 V DD x 1 x 2 x 3 f 7404 7408 7432 An implementation of f = x1x2 + x2x3 B&V3, Figure 3.22 20T3 COMP3222/9222 Implementation Technology L09/S27 A 4-bit, 2-register, 6-instruction 7400 series computer Wikipedia 20T3 COMP3222/9222 Implementation Technology L09/S28 Evolution of integrated circuit technology • Over time, chips have been classified according to their size – The earliest chips, such as 7400-series chips, comprise only a few logic gates – the technology used to produce these chips is referred to as small-scale integration (SSI) – Chips that included 10 to 100 gates represented medium-scale integration (MSI) – Until the mid-1980s, chips that were too large to qualify as MSI were classified as large-scale integration (LSI) • More recently, this classification scheme has lost practical value, as most integrated circuits contain many 1,000,000s, if not billions, of transistors – these are all made with what is referred to as very large scale integration (VLSI) technology – These devices support the trend in digital hardware to integrate as much circuitry as possible onto a single chip • This trend to ever greater levels of integration is driven by application needs, cost, performance, reliability and profit factors 20T3 COMP3222/9222 Implementation Technology L09/S29 The problem with fixed devices… • The functions provided by 7400-series parts are fixed and cannot be tailored to suit particular designs 20T3 COMP3222/9222 Implementation Technology L09/S30 • It is possible to manufacture chips that contain relatively large amounts of logic circuitry with a structure that is not fixed – Such devices were introduced in the 1970s and are called programmable logic devices (PLDs) – PLDs are general-purpose chips for implementing logic circuitry – They can be viewed as a black box containing logic gates and programmable switches to allow the gates to be interconnected as desired Logic gates and programmable switches Inputs (logic variables) Outputs (logic functions) Programmable logic device as a black box B&V3, Figure 3.24 20T3 COMP3222/9222 Implementation Technology L09/S31 f 1 AND plane OR plane Input buffers inverters and P 1 P k f m x 1 x 2 x n x 1 x 1 x n x n Programmable Logic Array (PLA) B&V3, Figure 3.25 Several types of PLDs are commercially available. The first developed was the programmable logic array (PLA). Based on the idea that logic functions can be implemented in sum-of-products form, a PLA comprises a collection of AND gates that feed into a set of OR gates. Product terms 20T3 COMP3222/9222 Implementation Technology L09/S32 f1 P1 P2 f2 x1 x2 x3 OR plane Programmable AND plane connections P3 P4 Gate-level diagram of a PLA B&V3, Figure 3.26 P1 = x1x2 P2 = x1x3 P3 = x1x2x3 P4 = x1x3 f1 = P1 + P2 + P3 = x1x2 + x1x3 + x1x2x3 f2 = P1 + P3 + P4 = x1x2 + x1x2x3 + x1x3 20T3 COMP3222/9222 Implementation Technology L09/S33 f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane AND plane P 3 P 4 More conventional schematic of the previous PLA B&V3, Figure 3.27 Commercial devices have typical sizes of 16 inputs, 32 product terms and 8 outputs. 20T3 COMP3222/9222 Implementation Technology L09/S34 f 1 P 1 P 2 f 2 x 1 x 2 x 3 AND plane P 3 P 4 Programmable Array Logic (PAL) B&V3, Figure 3.28 The presence of two switch planes in PLAs slows such devices down. Programmable array logic (PAL) overcomes this drawback by fixing the OR plane. They are therefore also less expensive to manufacture 20T3 COMP3222/9222 Implementation Technology L09/S35 f 1 To AND plane D Q Clock Select Enable Flip-flop Enhancing the flexibility of PAL outputs 20T3 COMP3222/9222 Implementation Technology B&V3, Figure 3.29 PAL OR-plane L09/S36 A PLD programming unit B&V3, Figure 3.30 (courtesy of Data IO Corp) Programming methods: • Fuse & anti-fuse • permanent • PROM, EPROM & EEPROM • slow & low density • SRAM • fast, but volatile • Flash • non-volatile, not as fast 20T3 COMP3222/9222 Implementation Technology L09/S37 PAL-like block I/ O b lo ck PAL-like block I/O block PAL-like block I/ O b lo ck PAL-like block I/O block Interconnection wires Structure of a complex programmable logic device (CPLD) B&V3, Figure 3.32 Commercial CPLDs have between 2 and 100 PAL-like blocks as seen here. 20T3 COMP3222/9222 Implementation Technology L09/S38 A section of a CPLD B&V3, Figure 3.33 PAL-like blocks for commercially available CPLDs typically have 16 macrocells with 5–20 inputs per OR gate. XOR used to optionally complement output. Three-states allow pins to be used as outputs or as inputs. Macrocell D Q D Q D Q PAL-like block (details not shown) PAL-like block 20T3 COMP3222/9222 Implementation Technology L09/S39 A field-programmable gate array (FPGA) • For cost and performance reasons, as few chips as possible are used to implement a design – 7400-series chips implement the equivalent of just a few two-input NAND gates (the prevalent metric for chip size) – An SPLD or CPLD macrocell represents about 20 equivalent gates; thus a PAL with 8 macrocells can accommodate a circuit that needs up to about 160 gates and a large CPLD with 500 macrocells can implement circuits of up to 10,000 equivalent gates – Modern FPGAs can be used to implement circuits of millions of equivalent gates in size B&V3, Figure 3.35 20T3 COMP3222/9222 Implementation Technology L09/S40 A two-input lookup table (LUT) as an FPGA logic cell (recall from Week 1) B&V3, Figure 3.36 (a) Circuit for a two-input LUT x 1 x 2 f 0/1 0/1 0/1 0/1 0 0 1 1 0 1 0 1 1 0 0 1 x 1 x 2 (b) f 1 x 1 x 2 x 1 x 2 + = (c) Storage cell contents in the LUT x 1 x 2 1 0 0 1 f 1 f 1 An n-input LUT serves as a small 2n address memory to implement an arbitrary Boolean function of n variables 20T3 COMP3222/9222 Implementation Technology L09/S41 f 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 x 2 x 3 x 1 A three-input LUT B&V3, Figure 3.37 20T3 COMP3222/9222 Implementation Technology L09/S42 Out D Q Clock Select Flip-flop In1 In2 In3 LUT Inclusion of a flip-flop in an FPGA logic block B&V3, Figure 3.38 20T3 COMP3222/9222 Implementation Technology L09/S43 A section of a programmed FPGA B&V3, Figure 3.39 f1 = x1x2 f2 = x2x3 f = f1 + f2 f = x1x2 + x2x3 0 1 0 0 0 1 1 1 0 0 0 1 x 1 x 2 x 2 x 3 f 1 f 2 f 1 f 2 f x 1 x 2 x 3 f In an FPGA, the LUT contents, routing switches and connection boxes are most commonly provided by SRAM cells 20T3 COMP3222/9222 Implementation Technology L09/S44 Custom chips • The key factor that limits the size of a circuit that can be accommodated in a PLD is the presence of the programmable switches • Although the switches afford PLDs their flexibility, they consume significant amounts of space and thus lead to increased cost, increased power consumption and reduced speed • To provide the largest number of logic gates, highest circuit speed or lowest power, a so-called custom chip can be manufactured • Whereas PLDs are prefabricated and available off-the-shelf, custom chips are created from scratch – the designer has complete flexibility to determine the number of transistors, their placement, and how they are to be interconnected • This enormous design effort leads to significant expense, and thus they are only produced when standard parts do not meet requirements or the quantity that is to be sold justifies the cost – Examples of products usually realized as custom chips include: microprocessors, memory chips, GPUs, FPGAs, WiFi transceivers, digital broadcast receivers, engine management units,… A section of two rows in a standard-cell chip • When the designer doesn’t need complete flexibility over the layout of individual transistors, a technology known as standard cells can be used • Chips made using this technology are also called application-specific integrated circuits (ASICs) • A standard cell design uses standard gates available from a library and is thus mostly concerned with their interconnection rather than the layout of transistors to create the cell B&V3, Figure 3.40 f 1 f 2 x 1 x 3 x 2 20T3 COMP3222/9222 Implementation Technology L09/S46 A sea-of-gates gate array B&V3, Figure 3.41 In gate array technology, a predefined array of gates is prefabricated onto the silicon wafer. The designer is then only concerned with the interconnections that are required to implement the design. These are added in a late fabrication step. Such devices are referred to as mask programmable. 20T3 COMP3222/9222 Implementation Technology L09/S47 The logic function f1 = x2x3+x1x3 in a gate array B&V3, Figure 3.42 f 1 x 1 x 3 x 2 20T3 COMP3222/9222 Implementation Technology L09/S48