COMP3222/9222 Digital Circuits & Systems
3. Number Representation & Arithmetic Circuits
Number Representation & Arithmetic Circuits
Objectives
• [Review] representation of numbers in computers
• Circuits for performing arithmetic operations
• Performance issues in large circuits
– The consequences of architectural decisions
• VHDL for specifying arithmetic circuits
• Work through some problems from the first 3 lectures
during Wednesday’s lecture
21T3 COMP3222/9222 L03/S2
Number Representation & Arithmetic Circuits
Unsigned integer representation
• Numbers that are positive only are called unsigned
• Numbers that can be negative are called signed
• Unsigned binary numbers are represented using the
positional number representation as in
B = bn-1bn-2…b1b0
which is an integer that has the value
V(B) = bn-1 x2n-1 + bn-2 x2n-2 + … + b1 x21 + b0 x20
with bi Î {0, 1}
• Note that the positional number representation can be
used for any radix r, in which the unsigned number
K = kn-1kn-2…k1k0
has the value
with ki Î {0, 1, .., r-1}
i
1n
0i
i 2b ´=å
–
=
å
–
=
´=
1n
0i
i
i rkV(K)
20T3 COMP3222/9222 L03/S3
Numbers in different systems
• Apart from radix 10 (decimal) and
2 (binary), radices 8 (octal) and 16
(hexadecimal, or simply “hex”) are
useful
• Octal & hexadecimal are useful
shorthand notations for binary
numbers, which are predominantly
used in computers
– A binary number is converted into
octal (hex) by taking groups of
three (4) bits, starting from the
least significant bit, and replacing
them with the corresponding octal
(hex) digit
– Conversion from octal (hex) to
binary requires that each digit be
replaced by the corresponding
three (4) bits denoting the same
value
• Revise decimal è binary
conversion if unsure
Note the need to introduce symbols
‘A’ through ‘F’ in hex in order to
represent the digits 10 through 15.
L03/S4Number Representation & Arithmetic Circuits
Number Representation & Arithmetic Circuits
Binary addition – the half-adder circuit
Note that the truth table
a) Is symmetric w.r.t. x and y, and
b) Converts the unary value xy into binary value cs
21T3 COMP3222/9222 L03/S5
Exclusive-OR
(XOR) function
s = x y + x y
c = x y
Exclusive-OR (XOR) gate
• In general, this requires at position i the addition of
three bits (two inputs and a carry-in from position i-1)
and results in a sum bit and a carry-out bit for the next
(more significant) position to the left
Number Representation & Arithmetic Circuits
Generated carries
15( ) 10
10( ) 10
25( ) 10
0 1 1 1 1
0 1 0 1 0
1 1 1 0
1 1 0 0 1
Binary addition of more than 2 bits
20T3 COMP3222/9222
X x 4 x 3 x 2 x 1 x 0 =
Y + y 4 y 3 y 2 y 1 y 0 =
S s 4 s 3 s 2 s 1 s 0 =
C c4 c3 c2 c1 =
L03/S6
Number Representation & Arithmetic Circuits
The full-adder circuit
0
0
0
1
0
1
1
1
c i 1 +
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x i y i c i
(a) Truth table
0
1
1
0
1
0
0
1
s i
(c) Circuit
c i 1 +
s i
c i
x i
y i
FA
c i
x i
y i
s i
c i 1 +
(d) Graphical symbol
20T3 COMP3222/9222
Consider the addition
of two bits and a
carry in at each bit
position, resulting in a
sum bit and a carry
out
00 01 11 10
0
1
x i y i
c i
1
1 1 1
c i 1 + x i y i x i c i y i c i + + =
00 01 11 10
0
1
x i y i
c i
1
1
1
1
(b) Karnaugh maps
si = (xi yi + xi yi )ci + (xi yi + xi yi )ci
= (xi Å yi )ci + (xi Å yi )ci
= (xi Å yi ) Å ci
a.k.a. the “odd” function
L03/S7
HA
HAs
c
s
c
c i
x i
y i
c i 1 +
s i
c i
x i
y i
ci+1
si
(a) Block diagram
(b) Detailed diagram
Decomposed full-adder
= ciÅ(xi Å yi)
= ci xi + ciyi + xiyi
Note that due to circuit resistance and capacitance, gates have a signal
“propagation delay” associated with them
Q1: What are the gate delays in computing si and ci+1?
Q2: AFTER si and ci+1 have settled, what effect does changing any input have?
• Just as in manual decimal addition, binary addition can be performed by
adding pairs of bits together starting at the least-significant bit (l.s.b.) po-
sition – a carry-out of position i is added to the operands in position i+1
• When the operands X and Y are applied to the adder, it takes some time before
the output S is valid because the carries have to be determined first
– If the time to produce the carry-out from the l.s.b. is Dt, and this delay is identical for
all adder stages, then the delay for the carry-out to be produced from the m.s.b. (most
significant bit) is nDt
– The adder derives its name from the manner in which carries ripple through the adder
from right to left [imagine changing Y = 0..00 → 0..01 after adding Y to X = 01..1]
FA
x n – 1
c n c n 1 –
y n 1 –
s n 1 –
FA
x 1
c 2
y 1
s 1
FA
c 1
x 0 y 0
s 0
c 0
m.s.b. position l.s.b. position
An n-bit ripple-carry adder
Number Representation & Arithmetic Circuits
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS
BEGIN
s <= x XOR y XOR Cin ; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ; END LogicFunc ; VHDL code for a full-adder 20T3 COMP3222/9222 L03/S10 VHDL code for a four-bit adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END fulladd ; ARCHITECTURE LogicFunc OF fulladd IS BEGIN s <= x XOR y XOR Cin ; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ; END LogicFunc ; LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY adder4 IS PORT ( Cin : IN STD LOGIC ; x3, x2, x1, x0 : IN STD_LOGIC ; y3, y2, y1, y0 : IN STD_LOGIC ; s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL c1, c2, c3 : STD_LOGIC ; COMPONENT fulladd PORT ( Cin, x, y: IN STD_LOGIC ; s, Cout: OUT STD_LOGIC) ; END COMPONENT ; BEGIN stage0: fulladd -- e.g. positional association PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: fulladd -- e.g. named association PORT MAP ( Cin => c3,
Cout => Cout,
x => x3,
y => y3,
s => s3 ) ;
END Structure ;
Subcomponent can also appear
in a separate file, often in the “work-
ing” (current project) directory
Need to include ieee.std_logic
library before each entity
declaration
Need to include ieee.std_logic
library before each entity
declaration within a source file
Component declaration
Component instantiations; Note:
two port association methods
20T3 COMP3222/9222
Declare internal
wires/signals
L03/S11
Number Representation & Arithmetic Circuits
• Avoids need to declare the component in the
architecture part
• Allows component to be reused across multiple projects
• The package declaration can appear at the end of the
source file containing the component(s)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
…
— your component descriptions (entities & architectures)
…
PACKAGE fulladd_package IS
COMPONENT fulladd
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END COMPONENT ;
END fulladd_package ;
Declaration of a user-defined package
20T3 COMP3222/9222 L03/S12
Number Representation & Arithmetic Circuits
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ; — user-defined package in current,
— “working” directory eliminates need to
ENTITY adder4 IS — explicitly declare fulladd component
PORT ( Cin : IN STD_LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ;
y3, y2, y1, y0 : IN STD_LOGIC ;
s3, s2, s1, s0 : OUT STD_LOGIC ;
Cout : OUT STD_LOGIC ) ;
END adder4 ;
ARCHITECTURE Structure OF adder4 IS
SIGNAL c1, c2, c3 : STD_LOGIC ;
BEGIN
stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;
stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;
stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;
stage3: fulladd PORT MAP (
Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;
END Structure ;
Instantiation of component using package
L03/S13
Number Representation & Arithmetic Circuits
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Cout : OUT STD_LOGIC ) ;
END adder4 ;
ARCHITECTURE Structure OF adder4 IS
SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;
BEGIN
stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ;
stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ;
stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ;
stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ;
END Structure ;
Use of multibit signals
Declaration of signals rep-
resenting numeric values
Declaration of collected, unre-
lated or non-numeric signals
20T3 COMP3222/9222 L03/S14
Number Representation & Arithmetic Circuits
bn 1– b1 b0
Magnitude
m.s.b.
(a) Unsigned number
bn 1– b1 b0
Magnitude
Sign
(b) Signed number
bn 2–
0 denotes
1 denotes
+
– m.s.b.
Signed numbers
20T3 COMP3222/9222 L03/S15
Number Representation & Arithmetic Circuits
Potential signed number representations
• Sign and magnitude
– Use the same positional number representation as for
unsigned numbers with a sign bit in the left-most position
• 1’s complement
– Derive an n-bit negative number K1 by subtracting the equivalent
positive number P from 2n – 1 i.e. K1 = (2n – 1) – P
– Equivalent to flipping every bit
• 2’s complement (preferred, as we shall see)
– Derive an n-bit negative number K2 by subtracting the equivalent
positive number P from 2n i.e. K2 = 2n – P = K1 + 1
– Algorithm for deriving 2’s complement:
• Given a signed number B = bn-1bn-2…b1b0, its 2’s complement
K2 = kn-1kn-2…k1k0 can be obtained by examining the bits of B from
right to left and taking the following action:
copy all bits of B that are 0 and the first bit that is 1;
then simply complement all the remaining bits on the left
20T3 COMP3222/9222 L03/S16
Number Representation & Arithmetic Circuits
Interpreting B=b3b2b1b0 as a signed integer
• Note the two
representations for
zero in the sign and
magnitude and 1’s
complement forms
• Note also the larger
range that can be
represented using 2’s
complement
20T3 COMP3222/9222 L03/S17
Number Representation & Arithmetic Circuits
Addition with sign and magnitude rep.
• If both operands have the same sign, then the addition
is simple – add the magnitudes and preserve the sign
– This is only trouble free if the sum can be represented given
the number of bits available for the magnitude
• If the operands have opposite signs, the magnitude of
the smaller number has to be subtracted from the
magnitude of the larger one
– Logic for comparing and subtracting numbers is also needed
– Hence unattractive for use in computers
20T3 COMP3222/9222 L03/S18
• While generating a negative number is easy, sometimes
a correction is involved in the addition
– Addition then takes twice as long as for two unsigned numbers
Number Representation & Arithmetic Circuits
++
1 1 0 0
1 0 1 0
0 0 1 0
0 1 1 1
0 1 0 1
0 0 1 0
++
0 1 1 1
1 0 1 0
1 1 0 1
0 0 1 0
0 1 0 1
1 1 0 1
1
1
0 0 1 1
1
1
1 0 0 0
2+( )
5–( )
3-( )
+
5–( )
7–( )
+ 2–( )
5+( )
2+( )
7+( )
+
5+( )
3+( )
+ 2–( )
1’s complement addition
20T3 COMP3222/9222 L03/S19
Number Representation & Arithmetic Circuits
++
1 1 0 1
1 0 1 1
0 0 1 0
0 1 1 1
0 1 0 1
0 0 1 0
++
1 0 0 1
1 0 1 1
1 1 1 0
0 0 1 1
0 1 0 1
1 1 1 0
11
ignore ignore
5+( )
2+( )
7+( )
+
5+( )
3+( )
+ 2–( )
2+( )
5–( )
3–( )
+
5–( )
7–( )
+ 2–( )
2’s complement addition
• Straightforward addition not involving complications
20T3 COMP3222/9222 L03/S20
Number Representation & Arithmetic Circuits
–
0 1 0 1
0 0 1 0
5+( )
2+( )
3+( )
–
1
ignore
+
0 0 1 1
0 1 0 1
1 1 1 0
–
1 0 1 1
0 0 1 0–
1
ignore
+
1 0 0 1
1 0 1 1
1 1 1 0
5–( )
7–( )
2+( )–
0 1 0 1
1 1 1 0
5+( )
7+( )
– +
0 1 1 1
0 1 0 1
0 0 1 02–( )
–
1 0 1 1
1 1 1 0– +
1 1 0 1
1 0 1 1
0 0 1 02–( )
5–( )
3–( )
2’s complement subtraction
• Most readily done by negating
the subtrahend and adding it to
the minuend
– Involves finding 2’s
complement of the subtrahend
and then performing addition
• As we ignore carry-outs of the
m.s.b., the same adder circuit
can be used for both addition
and subtraction
20T3 COMP3222/9222 L03/S21
Good design rule:
Develop circuits to be as flexible as possible and exploit common
portions for as many tasks as possible
– Minimizes the number of gates needed and the wiring complexity
Number Representation & Arithmetic Circuits
s 0 s 1 s n 1 –
x 0 x 1 x n 1 –
c n n -bit adder
y 0 y 1 y n 1 –
c 0
Add ⁄ Sub
control
Adder/subtractor unit
a 0 a 1 a n 1 – b 0 b1 b n 1 –
0 Þ B = y;
c0 = 0;
S = A + B + 0;
= x + y;
1 Þ B = y [1’s comp.]
= (2n – 1) – y;
c0 = 1;
S = A + B + 1;
= x – y; [2’s c]
21T3 COMP3222/9222
More generally, (mech) components, (SW) functions, etc.
L03/S22
XOR gates act
as conditional
inverters
Number Representation & Arithmetic Circuits
Performance issues
• The speed of a circuit is limited by the longest delay
along the paths through the circuit
– In the case of the adder/subtractor circuit of slide L03/S22, the
longest delay is along the path from input y0 through the XOR
gate and through the carry circuit of each adder stage
• In digital circuits, the longest delay is referred to as the
critical-path delay, and the path that causes this delay is
called the critical path
• Better performance can be achieved using faster
circuits by either:
1. Using superior gate technology (process/technology
innovation), or
2. Changing the overall structure of a functional unit (architectural
innovation).
20T3 COMP3222/9222 L03/S23
• Carry propagation delay can be reduced by quickly
evaluating the carry-in for each stage
• Recall, the carry-out for stage i can be realized as:
ci+1 = xi yi + xi ci + yi ci
which can be factored as:
ci+1 = xi yi + (xi + yi)ci
and rewritten as:
ci+1 = gi + pi ci (1)
where
gi = xi yi carry generated when both input bits are 1
pi = xi + yi carry propagated when either input bit is 1
Number Representation & Arithmetic Circuits
Fast addition: Carry-lookahead addition
c i 1 +
s i
c i
x i
y i
c i 1 +
s i
c i
x i
y i
20T3 COMP3222/9222 L03/S24
Number Representation & Arithmetic Circuits
Carry-lookahead addition
• Expanding the previous expression in terms of stage
i-1 gives:
ci+1 = gi + pi ci
= gi + pi (gi-1 + pi-1 ci-1)
= gi + pi gi-1 + pi pi-1 ci-1
ci+1 = gi + pi gi-1 + pi pi-1 gi-2 + …
+ pi pi-1 … p2 p1 g0 + pi pi-1 … p1 p0 c0 (2)
which represents a two-level AND-OR circuit (after the
gi’s and pi’s are calculated) in which ci+1 is evaluated
more quickly.
• An adder based on this expression is called a carry-
lookahead adder
20T3 COMP3222/9222 L03/S25
• Replaces one
AND gate in FA
circuit (L03/S7)
with an OR gate
• Critical path
length (shown in
red) 2n+1 gates:
– All gi & pi
signals
available after
1 gate delay
– Each stage
adds 2 more
gate delays to
compute ci+1
Number Representation & Arithmetic Circuits
x 1 y 1
g 1 p 1
s 1
Stage 1
x 0 y 0
g 0 p 0
s 0
Stage 0
c 0 c 1 c 2
A ripple-carry adder based on L03/S24 (1)
ci+1 = gi + pi ci
20T3 COMP3222/9222 L03/S26
x 1 y 1
g 1 p 1
s 1 s 0
c 2
x 0 y 0
c 0
c 1
g 0 p 0
Carry-lookahead adder based on L03/S25 (2)
ci+1 = gi + pi gi-1 + pi pi-1 gi-2 +…+ pi pi-1…p2 p1 g0 + pi pi-1…p1 p0 c0
• All carries produced
at the same time
after 3 gate delays
• All sum bits
computed in 4 gate
delays i.e. 1 gate
delay after carries
determined
• BUT, the complexity
grows at every stage
– 2 more wires
enter/leave per
stage
– 1 more AND gate
with one more input
per stage
– One more input to
OR gate per stage
20T3 COMP3222/9222 Number Representation & Arithmetic Circuits L03/S27
Number Representation & Arithmetic Circuits
• The complexity of an n-bit CLA grows rapidly with n
• Thus, use a hierarchical approach to implement large
adders
• For example, split a 32-bit adder into four 8-bit blocks
– Each block can be a CLA
– Interconnect blocks either in ripple-carry fashion:
Block
x31 24–
c32 c24
y31 24–
s31 24–
x15 8–
c16
y15 8–
s15 8–
c8
x7 0– y7 0–
s7 0–
c03
Block
1
Block
0
Carry-lookahead adder (CLA) with ripple-carry
between blocks
20T3 COMP3222/9222
Q: What is the critical path delay of this adder architecture?
L03/S28
Number Representation & Arithmetic Circuits
Block
x 15 8 – y 15 8 – x 7 0 – y 7 0 –
3
Block
1
Block
0
Second-level lookahead
c 0
s 7 0 –
P 0 G 0 P 1 G 1 P 3 G 3
s 15 8 –s 31 24–
c 8 c 16c 32
x 31 24– y 31 24–
c 24
Hierarchical carry-lookahead addition
…or using a second level of carry-lookahead:
20T3 COMP3222/9222 L03/S29
Number Representation & Arithmetic Circuits
Hierarchical carry-lookahead addition
• Uses a second (or more) levels of carry-lookahead to reduce the
time to produce carry signals between blocks
• Each block produces its own “block” generate and propagate signals
instead of carrys-outs – denote these as Gj & Pj for block j
• We then have for block 0
c8 = g7 + p7g6 + p7p6g5 + … + p7p6…p2p1g0 + p7p6…p1p0c0
= G0 + P0c0
with
G0 = g7 + p7g6 + p7p6g5 + … + p7p6…p2p1g0
P0 = p7p6…p1p0
Then
c16 = G1 + P1c8 = G1 + P1G0 + P1P0c0
and
c24 = G2 + P2G1 + P2P1G0 + P2P1P0c0
c32 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0
Note that higher numbered
Gj & Pj just renumber the
indices in the expressions for
G0 & P0
20T3 COMP3222/9222 L03/S30
Number Representation & Arithmetic Circuits
Hierarchical carry-lookahead addition
• The scheme takes 3 gate delays to produce the block
Gj and Pj functions
• It takes two more gate delays to produce the carry
signals c8, c16 & c24 (so, 5 gate delays in total)
• Two more gate delays are needed to produce the carry
signals for each bit within each block, and one more to
produce the sum bits
– After inputs change, a total of 8 gate delays are required to
compute the result (critical path computes s32)
– In contrast, a 32-bit ripple-carry adder needs 64 gate delays to
compute a result (critical path computes c32)
• IN PRACTICE:
– Gate fan-in/technology limitations force us to use multilevel
implementations of the generate and propagate functions unless
the blocking factor (number of bits added per block and
hierarchy level) is kept low [see p. 278 for gory details]
20T3 COMP3222/9222 L03/S31
Number Representation & Arithmetic Circuits
• When the carry-out of the m.s.b. ¹ carry-out of the sign-bit position,
overflow has occurred:
Overflow = c3 c4 + c3 c4 = c3 Å c4
• For n-bit numbers:
Overflow = cn-1 Å cn
++
1 0 1 1
1 0 0 1
0 0 1 0
1 0 0 1
0 1 1 1
0 0 1 0
7+( )
2+( )
9+( )
+
++
0 1 1 1
1 0 0 1
1 1 1 0
0 1 0 1
0 1 1 1
1 1 1 0
7+( )
5+( )
+ 2–( )
11
c4 0=
c3 1=
c4 0=
c3 0=
c4 1=
c3 1=
c4 1=
c3 0=
2+( )
7–( )
5–( )
+
7–( )
9–( )
+ 2–( )
Detecting overflow
20T3 COMP3222/9222 L03/S32
Number Representation & Arithmetic Circuits
Design of arithmetic circuits using
schematic capture
• Use of Altera’s Library of Parameterized Modules
– Bit width and signed/unsigned representation controllable
• Here parameterized for 16-bit wide addition
20T3 COMP3222/9222 L03/S33
Number Representation & Arithmetic Circuits
Timing simulation of an LPM adder
• Note the delay observed in updating the sum when an
input changes
– A period of glitching in the S output occurs as carries ripple
through the adder
20T3 COMP3222/9222 L03/S34
• Note use of std_logic_signed package
– Defines arithmetic ops on signed data types
– std_logic_unsigned does so for data of type unsigned
– LPM component of the required size automatically inferred
Number Representation & Arithmetic Circuits
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
ENTITY adder16 IS
PORT ( X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END adder16 ;
ARCHITECTURE Behavior OF adder16 IS
BEGIN
S <= X + Y ; -- maths ops +, - and * are synthesized by most tools END Behavior ; Behavioural code for a 16-bit adder 20T3 COMP3222/9222 L03/S35 Number Representation & Arithmetic Circuits LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout, Overflow : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + (‘0’ & Y) + Cin ; -- note concatenation operator used S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ; END Behavior ; Accessing the internal signals C(15) 20T3 COMP3222/9222 L03/S36 Number Representation & Arithmetic Circuits ENTITY adder16 IS PORT ( X, Y : IN INTEGER RANGE -32768 TO 32767 ; S : OUT INTEGER RANGE -32768 TO 32767 ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ; Using inbuilt INTEGER signals • Does not require library since INTEGER is an inbuilt type • But, accessing internal signals, so as to determine overflow, is impossible 20T3 COMP3222/9222 L03/S37