NYU Tandon School of Engineering Spring 2022, ECE 6443 Homework Assignment 1
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[released Saturday February 19th 2022] [due* Monday February 28th 2022, before 11:59 PM]
Please discuss HW assignments with other colleagues taking the class. Please do not share your solutions with other colleagues in the class. Please use the Brightspace portal to upload your completed HW as a single PDF document
The purpose of this HW assignment is to increase your familiarity with the device parameters in the newly installed ASAP 7nm PDKs that we will be using for Circuit Design Assignments. This familiarity can help you build better circuit designs and choose trade-offs in the design that are unique to your application.
1. Using DC simulations, plot the Gate characteristics (Drain Current on Y-axis Vs Gate Voltage on X-axis) on a linear and log scale (Y-axis) of the following
Transistors whose models are available in the ASAP 7nm PDK provided. Assume a Supply Voltage, VDD = 0.7V and a width of ‘3 fins’ for each of the transistors (i) – (iii) and a width of 1 fin for SRAM NFET and a width of 1 fin for the SRAM PFET
(a) From the Gate characteristics, extract the VT of each of the Transistors for the 2 cases of VDS = 10mV and 0.7V
NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
Show the Values of VT using a Bar diagram for NFETs and PFETs
(b) From the Gate characteristics, extract the Subthreshold Swing of each of the Transistors for the 2 cases of VDS = 10mV and 0.7V
NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
Plot the Subthreshold Swing of NFETs and PFETs as a function of VT (using results from (a) above). Do you see a trend? If so, explain why this is so
(c) From the Gate characteristics, determine the Off-current (drain current when VGS =0) of each of the Transistors for the 4 cases of VDS = 10mV, 100mV, 400mV and 0.7V
NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
Plot the off-current of NFETs and PFETs as a function of VT (using results from (a) above)
Plot the off-current of NFETs and PFETs as a function of VDS (using results from (a) above) for each of the NFETs and PFETs – Does DIBL have any impact on this trend? justify your response with percentage increase of off-current with increase in VDS
(d) From the Gate characteristics, determine the On-current (drain current when VGS =0.7V) of each of the Transistors for the case of VDS = 0.7V
NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
Plot the on-current of NFETs and PFETs as a function of VT (using results from (a) above)
(e) Using the results from (c) and (d) above, calculate the on/off current ratio for each of the Transistors below for the case of VDS = 0.7V
NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
Plot the (on/off) current ratio of NFETs and PFETs as a function of VT (using results from (a), (c) and (d) above)
(f) From the Drain characteristics (plot Drain current (IDS) on Y-axis Vs Drain V oltage (VDS) on x-axis), determine the Output Resistance (VDS/IDS) when VGS, VDS =0.7V) of each of the Transistors
NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
Plot the output-resistance of NFETs and PFETs as a function of VT (using results from (a) above). Does this plot show any trend? Explain it if so.
SRAM cell:
2. Setup the schematic of the 6T SRAM cell as shown in the Figure above. Assume PFETs M3, M4 have widths of 1 fin, NFETs M5 and M6 have widths of 1 fin and NFETs M1 and M2 have widths of 2 fins. Assume VDD = 0.7V, WL=0.7V and BL, BLB = 0.7V when attempting to read data from the cell
(a) What is the read current from BLB precharged to 0.7V through M6 and M2? (assume M2’s gate terminal, driven by storage node Q is at 0.7V). Plot the
dependence of Read current on BLB voltage. If transistors M5 and M6 had a width of 2 fins what would be the read current?
(b) What is the total leakage current from the cell – assume BL and BLB are at 0.7V and WL=0V. Assume Q/QB (storage nodes are at 0V/0.7V or 0.7V/0V). You can measure this by inserting a 1 ohm resistor between the source terminals of M1 and M2 and the Ground terminal and measure current through the resistor.
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