Microsoft Word – CSSE4010_2021_final_exam_EX.docx
Semester Two Final Examinations, 2021 CSSE4010 Digital System Design
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This exam paper must not be removed from the venue
School of Information Technology and Electrical Engineering
EXAMINATION
Semester Two Final Examinations, 2021
CSSE4010 Digital System Design
This paper is for EX students with Zoom invigilation.
Examination Duration: 120 minutes
Reading Time: 10 minutes
Exam Conditions:
This is a Closed Book examination – specified written materials permitted
Casio FX82 series or a calculator on the UQ approved list
During reading time (= planning time) – students are encouraged to review and
plan responses to the exam questions
This examination paper will be released to the Library
Materials Permitted In The Exam Venue:
(No electronic aids are permitted e.g. laptops, phones)
One A4 sheet of handwritten or typed notes double sided is permitted
Materials To Be Supplied To Students:
None
Instructions To Students:
Provide answers on the exam paper in the space provided.
You must provide working of your answers and marks will be given not just for the final result but
also for the methods follow.
You must state any assumptions made during answering the questions.
Upload a scanned copy of the written answers to the upload section in Blackboard exam site.
Venue ____________________
Seat Number ________
Student Number |__|__|__|__|__|__|__|__|
Family Name _____________________
First Name _____________________
For Examiner Use Only
Question Mark
Total ________
Semester Two Final Examinations, 2021 CSSE4010 Digital System Design
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Question 1 [25 marks]
1. Represent the following decimal numbers in the given formats [4 marks]
a. (-52) in fixed-point 8-bit 2’s complement with no fractional bits
b. (-19.125) in fixed-point 8-bit 2’s complement with 3 fractional bits
c. 875 in 16-bit binary coded decimal
d. (-273) in decimal 4-digit 10’s complement
2. Consider the following two Boolean functions expressed in terms of min-terms and don’t
care terms
𝒇 =#𝒎(𝟏, 𝟑, 𝟏𝟓, 𝟖, 𝟗, 𝟏𝟎) + 𝑫(𝟕, 𝟏𝟐, 𝟏𝟑, 𝟏𝟏)
𝒈 =#𝒎(𝟏, 𝟏𝟓, 𝟖, 𝟗, 𝟏𝟎) + 𝑫(𝟎, 𝟓, 𝟕, 𝟏𝟑, )
a. Provide individually simplified minimal sum of product (SOP) expressions for each
function using K-maps and express the total gate cost as the sum of number of AND
gates, number of OR gates and number of wires used (you do not need to count the
NOT gates when computing the gate cost and you can assume that the inverted
version of the variables are available) [10 marks]
Semester Two Final Examinations, 2021 CSSE4010 Digital System Design
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b. Considering any common terms between f and g that can be shared, obtain
simplified versions of f and g using K-maps considering both functions. Express the
total gate cost and compare with your answer in part (a). [11 marks]
Semester Two Final Examinations, 2021 CSSE4010 Digital System Design
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Question 2 [25 marks]
1. Consider a combinational logic circuit which takes two 2-bit unsigned binary numbers as
inputs A=A1A0 and B=B1B0 and provides an output F =1 if and only if the product of the
two numbers is greater than or equal to 2. Provide a minimal product of sum (POS)
expression for this circuit and provide a VHDL description in data flow abstraction.
(6 marks)
Semester Two Final Examinations, 2021 CSSE4010 Digital System Design
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2. Using appropriate diagrams, compare and contrast an 8-bit ripple carry adder, carry look-
ahead adder, carry-select adder and a bit-serial adder taking into account their area and
time complexities. (10 marks)
Semester Two Final Examinations, 2021 CSSE4010 Digital System Design
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3. Show how you can use tri state buffers and a 3:8 decoder to produce an 8:1 multiplexer
(2 marks)
4. Based on Shannon’s expansion of Boolean functions, show how you can implement the
logic function 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∏𝑀(2,5,6,9,13,1) using an 8:1 multiplexer. Use A, B, C as
the select inputs of the multiplexer with A being the most significant bit and C being the
least significant bit. (4 marks)
Semester Two Final Examinations, 2021 CSSE4010 Digital System Design
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5. Briefly describe what is meant by static-0, static-1 and dynamic hazards in relation to
combinational circuits and explain using an example how you can overcome any of those
hazards (3 marks)
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Question 3 [25 marks]
1. Provide VHDL entity-architecture descriptions for the following sequential circuit building
blocks
a. D latch with active high enable (3 marks)
b. Positive edge-triggered J-K flip flop with active low synchronous clear (3 marks)
c. Negative edge triggered T flip flop with active low asynchronous clear (3 marks)
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2. You are required to design a bit-serial (unsigned) 8-bit magnitude comparator circuit. The
circuit takes two 8-bit numbers A and B, serially, and delivers three outputs to denote
A>B, A=B and A