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Digital Logic And Computing Systems
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Chapter 08 – Instruction Set Architecture Assembler
EEL3701C Fall 2022
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Department of Electrical & Computer Engineering
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Instruction Set Architecture (ISA)
Transistors
Logic Circuits
Micro Architecture
(Register-Transfer Level)
Instruction Set Architecture
HW/SW interface:
Define a set of instructions, needed to control the hardware (CPU)
instruction set architecture
The number and type of instructions depend on the application field
In general, instructions are designed to:
optimize the construction and operation of the underlying hardware
make the program readable and easy to understand
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Arithmetic
Memory Address and Data Transfer
Arithmetic Operations with a Constant
Logic Operations
Control Flow
Instruction Coding
Subprograms
Addressing Modes
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Computer Paradigms
Domain Specific Computers
Application Specific Processor (ASIP)
Max. Performance
Min. Flexibility
Array A, B: [1:n]
Real c = A*B;
for i=1 to n do
C = C + A[i]*B[i];
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Max Flexibility
Min Performance
Computer Paradigm
Controlpath
Instructions
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68000 familly
Intel MCS-51 (8056), MCS 96 (8xC196)
Embedded Processor (System on Chip)
Qualcom Snapdragon series
IBM PowerPC series
Soft Cores
ARM Cortex
General Purpose Computing
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A computer consists of
Processor + Memory + In/Output
Memory consists of fixed-length words
Data and Instructions
Processor consists of data path and control path
Data path + Control path = Central Processing Unit (CPU)
Program Counter (PC), store memory address of the next instruction
More Registers in data path
Operation on register much faster
Basic Structure
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Processor/Central Processing Unit (CPU)
Control Path
Instructions
Instruction-
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Execution Cycle
Instruction Fetch
Read Operand
Write Back
Instruction
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Instruction fetching
Control path
Instructions
Instruction-
Instruction Fetch
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Instruction decode
Control path
Instructions
Instruction-
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Read Operands
Control path
Instructions
Instructions-
Read Operand
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Control path
Instructions
Instructions-
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Result write back
Control path
Instructions
Instruction-
Write Back
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Next Instruction fetching
Control Path
Instructions
Instruction-
Instruction
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MIPS Arithmetic operations
Arithmetic Basic Instructions
Meaning MIPS Instruction
a = b + c add a, b, c
a = b – c sub a, b, c
All MIPS arithmetic instructions have 3 operands
Long expressions are divided by the compiler into small instruction sequences
a = b + c + d + e add a, b, c
add a, a, d
add a, a, e
Insertion of temporary variables by the compiler if needed
f = (g + h) – (i + j) add t0, g, h
add t1, i, j sub f, t0, t1
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MIPS Arithmetic operations
MIPS arithmetic operations can be executed only with registers
32 general purpose registers, each with 32 bits
Datatype with 32-bit is called a word
A convention defines how registers are named and how they should be used
8 registers for variables of the source code: $s0, $s1,…, $s7
8 registers for temporary variables: $t0, $t1,…, $t7
Compiler (assembler programmer) doesn’t have to know this convention
Convention is important for assembled programs to work together
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MIPS Arithmetic operations
Assembling the following java (C/C++)- instructions:
f = (g + h) – (i + j)
Assumption: variables g, h,i and j are in registers $s1, $s2, $s3, $s4. Result f will be store in register $s0.
add $t0, $s1, $s2 # $t0=g+h
add $t1, $s3, $s4 # $t1=i+j
sub $s0, $t0, $t1 # f=(g+h)-(i+j)
The symbol # is used to place comments, from # until the end of the line
Limited number of registers: not enought to hold all variable of a program
variables, program, arrays are store in memory
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MIPS Memory Addressing
Memory is addressed byte-wise
The memory large 1-dimensional array of bytes
Lowest address is 0
How is a word (4 Bytes) stored in memory?
MIPS uses “Big-Endian” convention:
MSB of the word is at the lowest by address
A word is accessed with the address of it’s highest byte
Alignment restriction: Word address must be a multiple of 4
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Big Endian vs. Little Endian
Byte-Addresses
Big Endian
Byte-Addresses
Little Endian
32-bit Word:
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MIPS Data Transfer Operations
Data can be copied between memory and registers only with data transfer instructions
lw (load word)
sw (store word)
Example: java (C/C++)-Instruction: A[12] = h + A[8]
Assumption: A is an array of words. The variable h is in register $s2, the base address of A is register $s3
lw $t0, 32($s3) # $t0=Memory[$s3+32]
add $t0, $s2, $t0 # $t0=h+A[8]
sw $t0, 48($s3) # Memory[$s3+48]=$t0
Base register
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MIPS Arithmetic Operationen
How do we perform the arithmetic operation a = a + 3 ?
We can store the constant in memory, then use the lw to copy in register
Assumption: variable a is in register $s1. Constant 3 in memory at address store in $t1
lw $t0, 0($t1) # $t0=3
add $s1, $s1, $t0 # a=a+3
Because arithmetic with constants is so common, MIPS ISA has a special instruction for that:
addi (add immediate)
addi $s1, $s1, 3 # $s1=$s1+3
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MIPS Logic operations
Logic operations can only be executed with registers
Shift operations
sll (shift left logical)
srl (shift right logical)
sll $t2, $s0, 4 # $t2=$s0 << 4 bit Logic operation and (bitwise AND) andi (bitwise AND immediate) or (bitwise OR) ori (bitwise OR immediate) nor (bitwise NOR DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING MIPS Logic Operations Assumption: $s0 store value 0x00000009 sll $s1, $s0, 2 # $s1=0x00000024=3610= 9 x 4 or $s1, $s1, $s0 # $s1=? andi $s1, $s1, 15 # $s1=? andi $s2, $s2, 0 # $s2=? nor $s2, $s2, $s1 # $s2=? DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING MIPS Branching Control Flow Machine/Assembler programs consist of a sequence of instructions Instruction are executed sequentially The program counter is incremented by 4 (word address) for each instruction Branch instructions are used to change program flow (if-then-else, loop) Conditional branch beq (branch if equal) bne (branch if not equal) Unconditional jump DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Translation if-then-else C-Program: Assembler Program: Assumption: variables f, g, h, i, j in $s0,$s1,$s2,$s3 and $s4 Else, Exit are Labels if (i==j) { f = g + h; f = g – h; bne $s3, $s4, Else # if (i!=j) goto Else add $s0, $s1, $s2 # f=g+h j Exit # goto Exit Else: sub $s0, $s1, $s2 # f=g-h Exit: ... DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Loop Translation C-Program: Assembler Program: Assumption: variables i,k in $s3,$s5. Base address of saved in $s6 while (save[i]=k){ i = i + 1; Loop: sll $t1, $s3, 2 # $t1=4*i add $t1, $t1, $s6 # $t1= Address of save[i] lw $t0, 0($t1) # $t0=save[i] bne $t0, $s5, Exit # if (save[i]!=k) goto Exit addi $s3, $s3, 1 # i=i+1 j Loop # goto Loop DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING MIPS Branching MIPS has no branching instruction that checks the conditions smaller than or bigger than. Instead, we use: slt (set less than) slti (set less than immediate) slt $t0, $s3, $s4 # if ($s3<$s4) $t0=1 else $t0=0 MIPS has a special register: $zero $zero is permanently set to 0. Assignments to $zero are ignored With register $zero and instructions beq, bne, slt and slti we can implement various conditions DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Instruction Format Instructions in assembler must be translated in machine instructions to be processed by the CPU Instructions must be code in binary Instruction coding add $t0, $s1, $s2 0x000010001100100100000000100000 All MIPS instructions have 32 bits Because different instructions have different number of operand, instructions are divided in three categories R-Type Instructions I-Type Instructions J-Type Instructions DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Instruction Format - R-Type Instruction format R-Type (Register-Format) is used for arithmetic and logic instructions op Operation code (OP-Code) rs First operand register rt Second operand register rd Result register shamt Shift amount funct Function, options for one operation add $t0, $s1, $s2 DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Instruction Format - I-Type Instructions format I-Type (Immediate-Format) is used for: Immediate version of arithmetic and logic operations, Data transfer instructions and conditional branching immediate Constant or Address Immediate value is a 16-bit signed number in two’s complement Values between -215 and +215-1 sw $s1, -4($s2) 1111111111111100 DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Instruction Format - J-Type Instruction format J-Type (Jump-Format) is used for unconditional jump target branch address The target is a 26-bit number that will be interpreted as word address DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Procedure (Subprograms) The control is transferred to the procedure (callee) The calling procedure executes until completion The control is transfer back to the main program (caller) MIPS-support for procedure (subprogram) execution Special register to secure the return address: $ra Jump instruction jal (jump and link) save return address in $ra and jumps to start address of the procedure jr (jump register) jumps to the provided in the register jr $ra jump to the return address in the main program DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Procedure (Subprograms) A procedure takes arguments as input and produces results. MIPS uses the following convention to pass arguments and results: 4 Registers for arguments: $a0,..., $a3 2 Registers for results: $v0,$v1 jal procA # $ra = PC + 4, goto procA procA: ... # first instruction of procA jr $ra # goto $ra DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING MIPS Addressing Modes Direct Addressing Register Address immediate is a 16-bit signed number range [-215, +215-1] DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING MIPS Addressing Modes Base Addressing DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING MIPS Addressing Modes PC-Relative Addressing address is 16-bit signed number Branch Instruction can be jump in a range of [-215, +215-1] Word addresses relative to PC DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING MIPS Addressing Modes Pseudo direct addressing address is 26-bit unsigned 226 Words addressable (256 MB) Concatenation with the upper 4 bits of the PC 230 Words addressable DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Summary: MIPS Operands DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Summary: MIPS Instructions DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Compiler, Assembler, Binder and Loader DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com