UART
Intro to Pipelining
Christopher Mar
Announcements
Computer Organization Exam is to be completed at home on 11/17 (it will be available for 24 hours)
Taken on Canvas using Respondus LockDown Browswer with webcam monitoring
Timed: 75 minutes
One double-sided sheet of notes (typed or handwritten allowed
To be taken individually
Announcements
Mandatory Practice Quiz
Not worth any points
If you do not take the practice quiz and there are technical issues that prevent you from taking the Computer Organization Exam, you will receive a zero on the exam
Short Video
What to think about while watching the video:
Which of the processors mentioned are you familiar with?
What technological changes have occurred since this presentation was made?
Single Cycle Disadvantages
Single instruction occupies entire datapath for one clock cycle
Clock speed must be slow enough to accommodate slowest instruction
May requires duplicate hardware
For example: separate ALU for arithmetic computation and branch address calculation
Ways To Speed Up Processor
Parallelism
Bypassing (short cuts)
Prediction
Caching
Drying:
We have 4 loads of laundry. Each load has 2 steps that take 1 hour to complete:
Washing:
Laundry Example
Sequential Laundry
5 PM
9
Load 1
Load 2
Load 3
10
8
7
6
11
Load 4
12
1 AM
8 hours for 4 loads
Pipelined Laundry
5 PM
9
Load 1
Load 2
Load 3
10
8
7
6
11
Load 4
12
1 AM
5 hours for 4 loads
Pipelining Terminology
Pipeline stage:
A step or device in the pipeline
The washer and dryer are our laundry pipeline stages
Throughput:
Total amount of tasks completed in a unit of time
Pipelining Terminology
Throughput Calculation:
Sequential:
4 loads / 8 hours = 0.5 loads per hour
Pipelined:
4 loads / 5 hours = 0.8 loads per hour
Pipelining Terminology
Latency:
Amount of time to complete one task
Latency in a pipeline is generally the same or slower than a single cycle processor
In the laundry example, latency was the same, throughput was increased
MIPS/PLP Pipeline Stages
Instruction Fetch (IF)
Current instruction is read from memory
Next instruction determined
MIPS/PLP Pipeline Stages
Instruction Decode (ID)
Instruction broken down into fields
Registers values read
Immediate field sign extended
Registers from final stage written back
MIPS/PLP Pipeline Stages
Execute (EX)
Branch comparison
ALU operation
Arithmetic instruction
Address offset calculation (branch, store word, or load word instruction)
MIPS/PLP Pipeline Stages
Memory Access (MEM)
Memory reads and writes occur
Branch comparison result and target address fed back to IF stage
MIPS/PLP Pipeline Stages
WB (Writeback)
Arithmetic result or memory read result fed back to register file in ID stage
Pipelined Datapath
ALU
PC
Add
4
Instruction Memory
M
u
x
IF/ID
Register File
Sign Extend
16
32
M
u
x
M
u
x
ID/EX
EX/MEM
Comp.
Branch
Taken
Data Memory
MEM/WB
M
u
x
Pipeline Control
WB
M
EX
WB
M
WB
Control
Genera-
tion
IF/ID
ID/EX
EX/MEM
MEM/WB
RegDst
ALUOp
ALUSrc
Branch
MemRead
MemWrite
MemtoReg
RegWrite
strip off signals for
execution phase
strip off signals for
write-back phase
strip off signals for
memory phase
Instruction