SCHOOL OF ENGINEERING DIGITAL SYSTEM DESIGN 4 ELEE10007
Exam Diet: April/May 2020 Duration: 48 hours Expected workload: Two Hours plus upload
Exam starts: 13:00 on 20/05/2020 Exam ends: 13:00 on 22/05/2020 All times are BST (UTC+1)
Before commencing work, please read the academic, formatting, scanning and uploading guidance.
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Examination information
• This paper consists of TWO sections.
• Candidates should attempt THREE questions, chosen as follows:
• Section A: ONE question. Attempt the whole section.
• Section B: Answer TWO out of the THREE questions. Only TWO out of three questions will be
marked. Candidates must indicate which two questions are to be marked if three questions have been answered. If no indication is provided, the examiner will mark the FIRST TWO questions answered.
Specific instructions
• Students should assume reasonable values for any data not given in a question, or not available on a datasheet, and should make any such assumption clear on their answer sheets.
• Students in any doubt as to the interpretation of the wording of a question, should make their own decision, and should state it clearly on their answer sheet.
• Write concise, complete answers. If a length limit is given, stay within it. Produce equations and diagrams to a good hand-drawn standard.
• This is an open book exam. This means you can freely access any printed or online materials to aid you in your answers. Online materials can include text, images, videos and data. You may NOT engage in interactions or discussions relating to the exam questions or examined subject matter in any form. Sharing the answers to this exam in any way, by any means and in any form is STRICTLY NOT allowed.
• Use only a standard calculator. Do not use computer-based spreadsheets, mathematical solvers, simulation tools, graphing calculators or any other tool which is interactive in nature, such as online mathematical equation solvers.
Technical instructions (For full details see the formatting guidance and how to upload your exam to learn)
• Write in dark blue or black ink on white or light-coloured A4 paper, or the nearest equivalent size; unlined,
lined, and graph paper are all acceptable, as are pages with holes for binding.
• Write on one side of the paper only. Start every question on a new page. Use portrait orientation.
• On every page, rule a horizontal line 2cm below the top. Clearly write above the line, leaving large spaces between characters, the QUESTION NUMBER (left side) and your EXAMINATION NUMBER (right side).
• Arrange your pages so that your answers are given in the same order as the question paper.
• Take clear individual pictures of each page and combine in a single PDF document according to the scanning
instructions.
• Name your file with the course code and your examination number, e.g. ENGI00000-B123456.pdf
• Check your file carefully then upload it in the ONLINE EXAM area for this course on LEARN.
• If you require technical support, contact
Special Items
Convenor of Board of Examiners: Professor R Examiner: Professor J Morrow and Dr Z OTE: Answers to questions in sections A and B should typically require no more than three (3) pages. Complete and concise answers will be rewarded accordingly. Answers that contain excessive superfluous material may be penalised.
SECTION A Question A1
a) Different performance characteristics of computer systems will be
important for different use cases. Consider the different requirements
for a gaming desktop computer and for a server in a cloud computing system. Describe which performance parameter would be most
important for each case, providing a definition for each parameter. (4)
b) Consider two different processor implementations, M1 and M2, using the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 1 GHz and M2 has a clock rate of 1.15 GHz. The average number of cycles for each instruction class and their frequencies (for a typical program) are as follows:
A 1 2 60% B 2 2 30% C 4 5 10%
(i) Calculate the average CPI (cycles per instruction) for each machine, M1, and M2. (2)
(ii) Calculate the average MIPS (millions of instructions per
second) ratings for each machine. (2)
(iii) You have been asked to increase the MIPS rating of the lower
rated machine to beat the higher rated machine by changing
the CPI of only one instruction class. Explain how one of the
“Eight Great Ideas” in computer architecture would help you
decide which instruction class you should change, and find the required CPI for this class. (4)
c) There are two main forms that a multiprocessor, parallel computing
system can take. Describe these different forms, with reference to the method of communication between the processors, and how this is organised. Suggest an advantage and disadvantage of each form,
and describe a possible application for each system. (8)
Instruction Class
Machine M1 – Cycles/Instruction Class
Machine M2 – Cycles/Instruction Class
ELEE10007 Digital System Design 4 – May 2020
SECTION B Question B1
a) There are two key reasons for using virtual memory systems, explain
each of these in detail, with reference to how the benefits of virtual
memory organisation are achieved. (4)
b) For each of the situations described below, state which form of locality this represents and describe how a cache memory is arranged to exploit it.
(i) A loop in a programme which reads and writes a particular
variable during each cycle around the loop. (2)
(ii) A programme which sequentially accesses items in a data
array structure. (2)
c) Consider a directly mapped cache for a processor with a 32 bit physical address (byte addressed) that has the following arrangement:
Tag Index Block + byte offset Bit 31…14 Bit 13…7 Bit 6…0
(i) Describe the cache organisation giving details such as the
block size, number of blocks and the total size of the storage. (3)
(ii) If the cache is rearranged to be 4-way set associative with the
same block size, describe the new address arrangement and discuss the expected effect of this change on the miss rate and
hit time of the cache? (4)
d) Multilevel caching is now standard in most advanced processors. Assume a processor with a base CPI (cycles per instruction) of 1.0, when there are no cache misses, and a clock rate of 2.9 GHz. It has separate L1 (level 1) data and instruction caches. The time taken to access main memory, including handling misses, is 90 ns.
(i) If the miss rate for the instruction cache is 2.5%, data accesses occur on 25% of instructions, and the data cache miss rate is
10%, calculate the total CPI if there is no L2 (level 2) cache. (2)
(ii) The processor will be redesigned to have a L2 cache added,
with shared space for instructions and caches, and a 5 ns
access time whether or not the access hits or misses. What is
the required global miss rate in order to reduce the CPI from
part d)(i) by half? Global miss rate is the total rate of misses to main memory, i.e., misses at both levels of cache. (3)
ELEE10007 Digital System Design 4 – May 2020
Question B2
State which addressing mode is used for the last of the instructions in the code fragment:
DONE: sw $s0 32($s2)
You should provide a suitable diagram to illustrate the physical implementation of the address generation, including the width
of all busses. (3)
Considering the following MIPS code:
LOOP: sll $s0, $s0, 2 0x2108FFFF
bge $s1, $t0, DONE
DONE: sw $s0 32($s2)
a) (i) The SECOND instruction is shown as machine code in hexadecimal code instead of assembly language. Use the
MIPS green-card to decode this instruction to the assembly language representation. (2)
(ii) What is the format of the SECOND instruction? (2)
b) Assume $s0 holds the initial value 0x00000001, $s1 holds the initial value 0x00000001, $s2 holds the initial value 0x00000100, $t0 holds the initial value 0x00000005. What is the value of $s0 after running the above instructions?
c) bge $s1, $t0, DONE is a pseudo-instruction,
(i) How does the MIPS assembler expand it to real instructions? (4)
(ii) Explain the reason of using pseudo-instructions in MIPS
instructions sets. (2)
(ii) Sketch the datapath with high-level abstractions of the
hardware elements that can run the last instruction; highlight
the ports used in these hardware elements. (4)
ELEE10007 Digital System Design 4 – May 2020
Question B3
Uncover the bug in Figure QB3, explain your answer. (2)
The single-clock-cycle pipelined processor architecture shown in Figure QB3 is used to execute the following MIPS code:
lw $s0, 20($t1) add $t2, $s0, $t0 sub $t4, $t2, $t3 sw $t4 20($t1)
What are the five pipeline stages? (1) Explain your answer. (4)
(ii) What is the width of the EX/MEM register in Figure QB3?
(ii) When forwarding is used, draw the pipeline diagram and any
How many stalls are needed when forwarding is used to
resolve the data hazard? Explain your answer. (2)
inserted stalls for running this MIPS code. (4) c) Assume running each pipeline stage costs 200 ps,
(i) Calculate the time needed to run the FIRST and SECOND instruction in above MIPS code. (2)
(ii) Calculate the total time needed to run the above MIPS code
with the pipelined execution, considering any stalls and
forwarding. (2)
(ii) Draw an adapted version of Figure QB3 showing the correct pipeline datapath. Recalculate the width of the EX/MEM
register in your adapted version. (3)
ELEE10007 Digital System Design 4 – May 2020
Figure QB3
ELEE10007 Digital System Design 4 – May 2020
END OF PAPER
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