UART
Jump and Branch Disassembly
Christopher Mar
Jump Instructions
2
Labels
Pointers to memory locations of instructions
Assembler replaces labels with the address of the instruction being pointed to
RAM Organization
Memory is byte addressable
Memory addresses are word aligned
A word contains 32-bits (4 bytes)
Each address is a multiple of 4
Two least significant bits of a word aligned address are always zero
RAM Organization
RAM occupies the address range:
0x10000000 to 0x10FFFFFC
0b0001
The first 4 bits of every RAM address are the same
Jump Instruction Format
4 most significant bits and 2 least significant bits always the same
Use first 4 bits of previous address
Truncate 2 least significant bits
CPU shifts address left two bits to restore 2 zeroes
opcode
immediate value
6 bits
26 bits
Calculate Jump Address
000010
00000000000000000000000110
6 bits
26 bits
PC = PC[31:28] + (imm << 2) = 0x10000000 + (0b110 << 2) = 0x10000000 + (0b11000) = 0x10000000 + 0x18 = 0x10000018 Jump Instruction Format Lecture Question If a jump instruction’s value is 0x08000010 and the jump instruction is located at 0x10000044, the address being jumped to is: 0x10000004 0x10000008 0x10000010 0x10000040 0x10000044 Jump-And-Link (jal) Same format as a jump instruction, but different opcode Saves the address that follows the branch delay slot of the jal instruction in $ra Lecture Question If a jump-and-link (jal) instruction is located at the address, 0x10000200, what address is saved in $ra when the instruction is executed? 0x10000200 0x10000201 0x10000202 0x10000204 0x10000208 Branch Instruction 12 Jump vs. Branch Jumps are intended to reach any instruction in RAM Instruction contains target instruction address rather than an offset Branches are intended to skip small sections of code Use an 16 bit offset from current address Branch Instructions 14 Branch Instruction Format The value in rs and rt indicate which registers to compare 5 bits can represent the numbers 0 to 31 PLP has 32 registers opcode rs 6 bits 5 bits rt 5 bits offset 16 bits Branch Instruction Format Offset is the signed value Represents the number of instructions from the branch delay slot address to the label address 2 least significant bits of the offset are truncated just as they are for the jump opcode rs 6 bits 5 bits rt 5 bits offset 16 bits Calculate Branch Offset Offset: 0xFFFD is the signed value -3 CPU shifts offset value left 2 bits for address offset Address offset: -12 ( = -3 << 2) Offsets can also be positive if the target label is after the current instruction 000101 01000 opcode rs 00000 rt 1111 1111 1111 1101 offset Branch Offset Lecture Question If a branch instruction’s value is 0x11090002 and the branch delay slot is located at the address, 0x10000044, the target branch address is: 0x10000008 0x10000010 0x10000044 0x10000048 0x1000004C Lecture Question If a branch instruction’s value is 0x11090002, what two register numbers are being compared (i.e. the value represented by the $rs and $rt fields)? $11 and $9 $2 and $3 $4 and $5 $8 and $9 None of the above Lecture Question If a branch instruction’s value is 0x15090003 and the branch instruction is located at the address, 0x10000034, the target branch address is: 0x1000003C 0x10000040 0x10000044 0x10000048 0x1000004C Lecture Question If the bne is taken, what address will be branched to? 0x10000008 0x1000000c 0x10000010 0x10000014 0x10000018 Parting Words Branches move relative to location of the branch itself Jumps provide the entire address