Digital Logic and Computer Systems
Final Exam
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Friday, April 17th, 2020
04:00 PM – 06:00 PM
Name: ______________________________________
Student ID: _________________________________
Instructions
• This exam will be proctored on Zoom. If you are not in Zoom from exam begin to submission, you
will not receive a grade.
• This is a completely open-note exam, including online resources; however, collaboration between
other students is strictly prohibited.
• Submission will be via Canvas as a PDF/document upload.
• Any form of taking this exam is acceptable. You may print it, write on notebook/copy paper, use a
tablet-stylus combination, etc. If you do not print it, clearly mark which question you are on.
• Ensure ALL work is visible and clearly legible! Write large and dark.
• This is an 8-page exam, including this title sheet. There are no blank pages (all pages have a
question).
Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Total
/08 /10 /08 /22 /18 /66, %
EEL 3701C – Final Exam Friday April 17th, 2020 4:00 PM – 6:00 PM
Problem I (Multiplication, 8 pts)
1. Use the Shift-and-Add algorithm to multiply the following numbers, given in two’s complement: -45 and
-18 (4 pts)
2. Compute the minimum cost (in term of number of additions/subtractions) of multiplying the two
positive numbers 11101110 and 101010100 using the following algorithms:
a. Shift-and-Add Algorithm (2 pts)
b. Booth’s Multiplication Algorithm (2 pts)
EEL 3701C – Final Exam Friday April 17th, 2020 4:00 PM – 6:00 PM
Problem II (Memory, 10 pts)
Assume that we have only 4×4 ROM memory modules available in our RTL component library. Using the
available memory components, sketch the internal design of an 8×6 ROM that stores the following values:
Address 2 6 0 7
Value 30 15 0 22
Unspecified addresses are don’t cares.
EEL 3701C – Final Exam Friday April 17th, 2020 4:00 PM – 6:00 PM
Problem III (Adder Components, 8 pts):
We want to implement a 64-bit adder using a library that contains 4-bit, 8-bit and 16-bit carry lookahead adder
components.
Your design must be uniform, i.e., you can only use all 4-bit adders, all 8-bit adders, OR all 16-bit
Provide the architecture of the adder with:
a. The minimum cost (in number of gates) (3 pts)
b. The minimum delay, assuming all gates have the same propagation delays pd
c. Can your design achieve minimal cost and delay simultaneously? (2 pts)
EEL 3701C – Final Exam Friday April 17th, 2020 4:00 PM – 6:00 PM
Problem IV (Control Path and Data Path Design, 22 pts)
Provide the architecture of a processor, specifically tailored to compute the following pseudocode algorithm:
Assume that the 4-bit data inputs (A and B) and outputs (C) are directly connected to the data path through
three different buses, IN_BUS_A, IN_BUS_B and OUT_BUS.
A computation starts with A and B placed on IN_BUS_A and IN_BUS_B and a start signal s set 1. The
controller will then process and set a done signal to 1 upon completion. Additionally, the controller will not
move back to the initial state until s = 0. Because the values on the input bus may change during the
computation, they need to be loaded into registers before starting.
a. Identify the data path components and their interconnections (5 pts)
Do not worry about the interior construction of the components themselves. State any assumptions you
make about your components.
b. Show the block diagram (control path + data path), showing all control and status signals between the
two, as well as any inputs and outputs to the system as a whole. (2 pts)
if (a < b) then c = a – b; c = a + b; EEL 3701C – Final Exam Friday April 17th, 2020 4:00 PM – 6:00 PM c. Design your controller as Moore automaton and show the implementation as microprogrammed unit. (This is not an empty page!) EEL 3701C – Final Exam Friday April 17th, 2020 4:00 PM – 6:00 PM Problem V (MIPS Processor, 18 pts) Given the single-cycle MIPS processor below, show the data value at the following annotated points A-F after the execution of the block of code in order The contents of register file, the data memory, and the instruction memory is as follows: Initial state of the program. All values are in decimal. (Question continued on next page) Addr. Instruction 100 sw $t1, 8($t0) 104 add $t1, $t1, $t1 108 beq $t1, $t1, EXIT 200 EXIT: … “…” – not relevant EEL 3701C – Final Exam Friday April 17th, 2020 4:00 PM – 6:00 PM Please provide all values in decimal in the tables below Remember: Do each part here as if all previous instructions have been run up to that point. For example, for the add instruction, show the state of the processor assuming that sw was already executed, and that add is about to run. Use an ‘X’ to signify if a signal is undefined. sw $t1, 8($t0) add $t1, $t1, $t1 beq $t1, 4t1, EXIT 程序代写 CS代考 加微信: powcoder QQ: 1823890830 Email: powcoder@163.com