CSE 362M Lab #5
CSE 362 LAB 5
INTRODUCTION
In this laboratory, you will create an embedded system based on a 128-bit version of the
RSRC used in Lab 0. You will modify the RSRC from Lab 0 to create the 128-bit CPU.
STEP -1
Create new versions of Table 1 and Table 2 in “The Really Simple RISC Computer” to
document the instruction format and abstract RTN, respectively, for your 128-bit RSRC.
The RSRC should be extended in the “natural way,” i.e., by extending the c1 and c2
constant fields with the OP code remaining in the most significant five bits of the 128-bit
instruction. All other constant fields, e.g., the branch condition field and the shift count
field, should use the least-significant bits in the instruction word and be extended as
needed.
STEP 0
Make a copy of the VHDL source files supplied for Lab 0. Replace the alu.vhd and
regfile.vhd files with the new versions supplied by the instructor. Modify each of the
RSRC VHDL files to implement a 128-bit version of the RSRC.
The alu.vhd and regfile.vhd files supplied with Lab 0 were written in a very
straightforward way. Extending these designs to 128-bit implementations would be
extremely painful. The replacement versions supplied by the instructor for use with this
laboratory use much more advanced VHDL coding techniques, allowing them to be
easily modified to any width easily once those coding techniques are understood.
STEP 1
Create a full 128-bit embedded system by carefully modifying the eprom.vhd, sram.vhd,
vga.vhd, and testbench.vhd files, taking into account the fact that instructions are now
128 bits long.
Implement 1K words of EPROM and SRAM as before, so that now with the longer word
size each occupies 16 KB of address space instead of 4 KB as before (each word in a
128-bit machine is 16 bytes long).
In the 32-bit embedded RSRC system, the VGA framestore occupies 2 MB of address
space, i.e., the actual framestore is 1024×512 words (1/2 MW) in size (only 640×480
pixels are visible). In embedded RSRC systems, just like in PCI systems, memory blocks
start on an address boundary that is a multiple of the memory block size, and in the
original embedded RSRC system the VGA framestore starts at address “2 MB.”
In your 128-bit embedded RSRC system, the framestore will be 8 MB in size (there will
be 16 bytes/pixel). Map the VGA framestore on the appropriate boundary.
STEP 2
Using your tables from STEP -1 as a guide, create a new eprom.vhd file by carefully
hand assembling a 128-bit version of the original Lab 0 assembly program. Remember
that the change in word size will change memory addresses, too. HINT: Replacing LAR
instructions with LA instructions will make the program easier to assembly.
STEP 3
Create a new Vivado project using your modified source files.
STEP 4
Synthesize your new design, and use any warning messages generated by the tool to help
identify as many errors as possible.
STEP 5
Simulate the 128-bit embedded RSRC system executing your hand-assembled 128-bit
code, fix any issues you identify during simulation startup, and make sure the register file
starts updating correctly.
It is almost guaranteed that, on the first attempt, your 128-bit embedded system will not
operate correctly. Use the simulator to identify and fix any problems with your 128-bit
embedded RSRC system. You should be able to see the RSRC start writing the VGA
framestore, DONE being asserted on each framestore write, etc.
STEP 6
Once you are convinced that your 128-bit embedded system works, recreate the
simulation of Lab 0 STEP 1 showing reg31 being updated for the first time. So that you
can compare the results to those of Labs 0, 1, and 2, force a clock with a 10 ns period and
assert RESET_L for 555 ns as you did before.
Take a screen shot of the properly zoomed waveform display showing reg31 being
updated with the (yellow) cursor positioned exactly at the instant reg31 is updated.
How do your results, with a 128-bit RSRC, compare to what you observed in Lab 0?
STEP 7
Implement your Vivado project, and generate a .BIT file you can submit for testing.
STEP 8
Submit the modified versions of Tables 1 and 2 from STEP -1, the “Lab 5” project folder
you generated in Step 3, the simulation screenshot .PNG file you created in STEP 6, and
the .BIT file you generated in Step 7 via Canvas for grading.
GRADING RUBRIC
Correctly modified Tables 1 and 2 from Step -1: 10%
Properly created “Lab 5” Vivado project folder from Step 3: 10%
Correctly implemented 128-bit embedded system VHDL: 60%
Simulation screen shot showing reg31 being updated properly at the correct time: 10%
Functioning .BIT file: 10%