Lab 5 Bullet Points
Lab 5
Bullet Points
William D. Richard, Ph.D.
Updated November 12, 2021
128-Bit Instruction Format
• See the associated synchronous lecture for discussion of how the 32-
bit instruction format must be extended to the new 128-bit format
• All 27 instructions must execute properly
• All 128-bit RSRC CPU designs submitted for grading will undergo extensive
testing and evaluation by the instructor
• The fact that the Lab 0 code runs and displays the proper color patterns on
the VGA display does not mean you will receive 100% on Lab 5
• Memory and I/O implementation errors may not be identified by the
simple Lab 0 test code
• This lab is not just about extending the instruction format!
Memory and I/O
• EPROM must maintain 1 KW of storage
• This implies moving from a 4 KB EPROM to a 16 KB EPROM
• The EPROM address space still starts at the bottom of memory
• SRAM must maintain 1 KW of storage
• This implies moving from a 4 KB SRAM to a 16 KB SRAM
• The SRAM address space still starts after the EPROM in the address space
• The VGA framestore must still have 524,288 words (only the bottom 9 bits
will be implemented as before)
• The VGA address space will be four times larger (in bytes), and the framestore must
map starting at an address that is a multiple of the framestore size (like PCI)
• Addresses issued by the RSRC are byte addresses
• This is consistent with the 32-bit RSRC, and it has many implications!
Simulation and Testing
• The reg31 simulation time must match the time from Lab 0
• You must also check that the VGA memory is actually updated
• The fact that reg31 updates in simulation does not guarantee your BIT file will
work: You must also look at writes to the framestore in simulation!
• Even if the framestore is written to in simulation, your BIT file may not
work when tested
• You should know by now that “but it works in simulation” means nothing
• On the other hand, if the framestore is not written to in simulation, you can
be sure your design will not work when tested
• The instructor will run additional test code on your 128-bit embedded
system to exhaustively test all aspects of your implementation