RSRC LAB 0 TESTBENCH BLOCK DIAGRAM
AND MEMORY MAP
Copyright William D. Richard, Ph.D.
Updated July 14, 2021
The RSRC lab 0 embedded RSRC CPU system consists of the following VHDL components/modules
implemented in the top-level VHDL file testbench.vhd:
0) DIGITAL CLOCK MANAGER
1) RESET_L SYNCHRONIZER CODE (ALWAYS!)
2) RSRC
3) EPROM
4) SRAM
5) VGA
A Digital Clock Manager (DCM) is used to create a 50 MHz clock for the RSRC from the 100 MHz FPGA
clock input (the bus-based RSRC will not run at 100 MHz in the Artix-7 FPGA on the Digilent
development board) and a 25 MHz clock for the VGA module. The DCM port map is included in the
testbench.vhd file, at the top, right after “BEGIN” in the architecture section. The 100 MHz clock
supplied by an external oscillator, called “clk,” is connected to pin E3 on the FPGA. The 50 MHz DCM
output clock is called “src_clk,” and the 25 MHz DCM output clock is called “vga_clk.”
The main inputs to the top-level testbench.vhd module are clk and reset_l (unsynchronized), and the
outputs are the signals that connect to an external VGA monitor.
A block diagram of the testbench.vhd “wrapper” is shown on the next page. This block diagram
corresponds accurately with the actual VHDL found in testbench.vhd, with only a few exceptions:
a) The DCM implemented in testbench.vhd is not shown in the diagram;
b) The READ.L and WRITE.H signals shown on the block diagram are accurate, but in the VHDL each sub-
module (SRAM, EPROM, and VGA) each have their own named version of these signals. But, the diagram
is accurate relative to functionality.
When implemented using the Vivado tools, the embedded RSRC CPU boots from the EPROM, can read
and write the SRAM, and can write to and read from the VGA module.
In lab 0, the RSRC runs a program from EPROM at boot that writes different “colors” to the VGA module
frame store repeatedly in an infinite loop.
The VGA module implements a 9-bit frame store mapped in the 32-bit RSRC memory map as shown on
the memory map below (a 4th zero bit is output for each color to match the dev board circuitry). As
shown on the memory map, the 4 KB EPROM is mapped to the very bottom of the memory address
space, and the 4 KB SRAM is placed immediately above the EPROM in the address space.
WRITE.H
4
4
4
READ.L
VGA_ENA
EPROM_CE.L
RESET_L_SYNC
D<31..0>
SRAM_CE.L
D<31..0>
A<11..2>
A<11..2>
EPROM
WRITE.L
READ.L
SRAM RSRC
DONE.H
WRITE.H
READ.H
A<31..13>
A<12>
READ.H
WRITE.H
SRC_CLK
SRC_CLK
10
32
32
A<31..0>
19
10
A<31..12>
READ.H
20
32
VGA_ENA
RESET_L_SYNC
VGA
SRC_CLK
VGA_CLK
A(20:2)
D<8..0>
A<31..22>
A<21>
10
LAB 0 RSRC MEMORY MAP
EPROM
4 KB
SRAM
4 KB
VGA
0000 0000H
0000 1000H = 4096
FFFF FFFFH
219 WORDS = 524288 WORDS = 2097152 BYTES
UNUSED ADDRESS SPACE
0000 2000H = 8192
0020 0000H = 2097152