MIPS Single-cycle Processor
Assignment Outline
This assignment is to test your understanding of the MIPS-Lite single-cycle processor
design presented in the lectures.
A sample Verilog code is available at Appendix A. You will need to add an Instruction
memory to the design and initialise it with your assembly code. The procedure for process
is given in the Appendix B.
Currently the memory initialization file of the instruction memory ROM is empty. You can
write the machine code of your instructions into the memory locations of the initialisation
file.
The assignment is to be undertaken in a series of steps which you should complete in
order. To ensure that it is your own work that is being assessed, Appendix C shows the
specific requirements for each student.
1. Write a programme to: [15 Marks]
a. Load the data stored in the X and Y locations of the data memory into the X and Y
registers.
b. Add the X and Y registers and store the result in the Z register.
c. Store the data from the Z register into the Z memory location.
d. Load the data in the Z memory location into the T register.
2. Simulate your program to show the contents of the X, Y, and T registers. [10 Marks]
3. Modify the program.mif file to simulate the operation of the BEQ instruction. [10 Marks]
4. Modify the design of the processor so that the Jump (J) instruction is implemented. [15
Marks] Modify the program.mif file to simulate the operation of the Jump instruction. [10
Marks]
5. Modify the designs so that the additional instructions given in the column “Design 1” is
correctly executed. [15 Marks]
6. Modify the program.mif file to simulate the operation of the additional instruction. [10
Marks]
7. Change the processor’s data bus width from 32 to the one indicated in the table. Repeat
the simulation of step 2 using your new processor. [15 Marks]
MIPS instructions’ reference data is provided.
Reports
Your report should include the following contents:
1. The MIPS code and how the corresponding machine code is decided.
2. Simulation waveforms for the PC, opcode, ALUResultOut, DReadData and relevant
registers (X, Y, T) must be annotated. You should clearly indicate why the simulations
show that the operation is correct or incorrect.
2. Description of the modifications made to the Verilog code for implementing the Jump
instruction. Highlight the changes made in the code.
3. Description of the modifications made to implement the additional instruction. Highlight
the changes made in the code.
4. Description of the modifications made to change the data bus width.
Submission Date
A single PDF file should be submitted to ICE by 2pm on Monday 6th December 2021
(Week 13). This file should be named as “surname_forename_A2.pdf”, e.g.
“Xu_Ming_A2.pdf”. The contents in each submission must be consistent with the tasks
assigned to a specific student; otherwise a zero mark will be awarded. There is no
demonstration lab session for this assignment.
Appendix A
// MIPS single Cycle processor originaly developed for simulation by Patterson
and Hennesy
// Modified for synthesis using the QuartusII package by Dr. S. Ami-Nejad. Feb.
2009
// Register File
module RegisterFile (Read1,Read2,Writereg,WriteData,RegWrite, Data1,
Data2,clock,reset);
input [4:0] Read1,Read2,Writereg; // the registers numbers to read or
write
input [31:0] WriteData; // data to write
input RegWrite; // The write control
input clock, reset; // The clock to trigger writes
output [31:0] Data1, Data2; // the register values read;
reg [31:0] RF[31:0]; // 32 registers each 32 bits long
integer k;
// Read from registers independent of clock
assign Data1 = RF[Read1];
assign Data2 = RF[Read2];
// write the register with new value on the falling edge of the clock if
RegWrite is high
always @(posedge clock or posedge reset)
if (reset) for(k=0;k<32;k=k+1) RF[k]<=32'h00000000;
// Register 0 is a read only register with the content of 0
else if (RegWrite & (Writereg!=0)) RF[Writereg] <= WriteData;
endmodule
//ALU Control
module ALUControl (ALUOp, FuncCode, ALUCtl);
input [1:0] ALUOp;
input [5:0] FuncCode;
output [3:0] ALUCtl;
reg [3:0] ALUCtl;
always@( ALUOp, FuncCode)
begin
case(ALUOp)
2'b00: ALUCtl = 4'b0010;
2'b01: ALUCtl = 4'b0110;
2'b10: case(FuncCode)
6'b 100000: ALUCtl = 4'b 0010;
6'b 100010: ALUCtl = 4'b 0110;
6'b 100100: ALUCtl = 4'b 0000;
6'b 100101: ALUCtl = 4'b 0001;
6'b 101010: ALUCtl = 4'b 0111;
default: ALUCtl = 4'b xxxx;
endcase
default: ALUCtl = 4'b xxxx;
endcase
end
endmodule
//ALU
module MIPSALU (ALUctl, A, B, ALUOut, Zero);
input [3:0] ALUctl;
input [31:0] A,B;
output [31:0] ALUOut;
output Zero;
reg [31:0] ALUOut;
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0
always @(ALUctl, A, B) begin //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
6: ALUOut <= A - B;
7: ALUOut <= A < B ? 1:0;
// .... Add more ALU operations here
default: ALUOut <= A;
endcase
end
endmodule
// Data Memory
module DataMemory(Address, DWriteData, MemRead, MemWrite, clock, reset,
DReadData);
input [31:0] Address, DWriteData;
input MemRead, MemWrite, clock, reset;
output [31:0] DReadData;
reg [31:0] DMem[7:0];
assign DReadData = DMem[Address[2:0]];
always @(posedge clock or posedge reset)begin
if (reset) begin
DMem[0]=32'h00000005;
DMem[1]=32'h0000000A;
DMem[2]=32'h00000055;
DMem[3]=32'h000000AA;
DMem[4]=32'h00005555;
DMem[5]=32'h00008888;
DMem[6]=32'h00550000;
DMem[7]=32'h00004444;
end else
if (MemWrite) DMem[Address[2:0]] <= DWriteData;
end
endmodule
// Main Controller
module Control
(opcode,RegDst,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUSrc,RegWrite);
input [5:0] opcode;
output [1:0] ALUOp;
output RegDst,Branch,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite;
reg [1:0] ALUOp;
reg RegDst,Branch,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite;
parameter R_Format = 6'b000000, LW = 6'b100011, SW = 6'b101011, BEQ=6'b000100;
always @(opcode)begin
case(opcode)
R_Format:{RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp}=
9'b 100100010;
LW: {RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp}=
9'b 011110000;
SW: {RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp}=
9'b x1x001000;
BEQ: {RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp}=
9'b x0x000101;
// .... Add more instructions here
default: {RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp}=
9'b xxxxxxxxx;
endcase
end
endmodule
// Datapath
module DataPath(RegDst, Branch, MemRead, MemtoReg, ALUOp, MemWrite,
ALUSrc, RegWrite, clock, reset, opcode,/* RF1, RF2, RF3,*/ALUResultOut
,DReadData);
input RegDst,Branch,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,clock, reset;
input [1:0] ALUOp;
output [5:0] opcode;
output [31:0] /*RF1, RF2, RF3,*/ ALUResultOut ,DReadData;
reg [31:0] PC, IMemory[0:31];
wire [31:0] SignExtendOffset, PCOffset, PCValue, ALUResultOut,
IAddress, DAddress, IMemOut, DmemOut, DWriteData, Instruction,
RWriteData, DReadData, ALUAin, ALUBin;
wire [3:0] ALUctl;
wire Zero;
wire [4:0] WriteReg;
//Instruction fields, to improve code readability
wire [5:0] funct;
wire [4:0] rs, rt, rd, shamt;
wire [15:0] offset;
//Instantiate local ALU controller
ALUControl alucontroller(ALUOp,funct,ALUctl);
// Instantiate ALU
MIPSALU ALU(ALUctl, ALUAin, ALUBin, ALUResultOut, Zero);
// Instantiate Register File
RegisterFile REG(rs, rt, WriteReg, RWriteData, RegWrite, ALUAin,
DWriteData,clock,reset);
// Instantiate Data Memory
DataMemory datamemory(ALUResultOut, DWriteData, MemRead, MemWrite, clock, reset,
DReadData);
// Instantiate Instruction Memory
IMemory IMemory_inst (
.address ( PC[6:2] ),
.q ( Instruction )
);
// Synthesize multiplexers
assign WriteReg = (RegDst) ? rd : rt;
assign ALUBin = (ALUSrc) ? SignExtendOffset : DWriteData;
assign PCValue = (Branch & Zero) ? PC+4+PCOffset : PC+4;
assign RWriteData = (MemtoReg) ? DReadData :
ALUResultOut;
// Acquire the fields of the R_Format Instruction for clarity
assign {opcode, rs, rt, rd, shamt, funct} = Instruction;
// Acquire the immediate field of the I_Format instructions
assign offset = Instruction[15:0];
//sign-extend lower 16 bits
assign SignExtendOffset = { {16{offset[15]}} , offset[15:0]};
// Multiply by 4 the PC offset
assign PCOffset = SignExtendOffset << 2;
// Write the address of the next instruction into the program counter
always @(posedge clock ) begin
if (reset) PC<=32'h00000000; else
PC <= PCValue;
end
endmodule
module MIPS1CYCLE(clock, reset,opcode, ALUResultOut ,DReadData);
input clock, reset;
output [5:0] opcode;
output [31:0] ALUResultOut ,DReadData; // For simulation purposes
wire [1:0] ALUOp;
wire [5:0] opcode;
wire [31:0] SignExtend,ALUResultOut ,DReadData;
wire RegDst,Branch,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite;
// Instantiate the Datapath
DataPath MIPSDP (RegDst,Branch,MemRead,MemtoReg,ALUOp,
MemWrite,ALUSrc,RegWrite,clock, reset, opcode, ALUResultOut ,DReadData);
//Instantiate the combinational control unit
Control MIPSControl
(opcode,RegDst,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUSrc,RegWrite);
endmodule Appdendix B
Inserting LPM ROM
Select MegaWizard Plug-In Manager from the tools menu and click on the Next button.
Select the ROM: 1-PORT and give a name to the output file. This name should be the same as the
one which has been used for Instruction memory instantiation in your Verilog code.
Select the width and depth of the memory.
Deselect the input and output registers.
Give a name to the memory initialisation file, e.g. Instruction.mif. You can use your name as the file name.
In this case you should edit the Verilog module name in the provided code.
Deselect the creation of the optional files and click on Finish button.
Click on the New icon and select the Memory Initialization File.
Input 32 for the Number of words and 32 for the Word size.
Now you can insert your machine code into the Instruction memory locations. You should be noted that this
memory is not byte oriented and addresses are incremented by one not by 4.
Appendix C: The tasks for each student
ID English Name
Memory
locations
(X,Y,Z,T)
Data
bus
size
Design
1508601 Ziming Zeng 3,4,5,6 24 Ori
1509753 Anyuan Fu 7,1,2,3 28 Andi
1509811 Jiacheng Zhang 4,5,6,7 20 Ori
1510093 Xinhang Lyu 1,2,3,4 24 Andi
1612586 Haoquan Kong 5,6,7,1 28 Ori
1716181 Yuhan Gu 2,3,4,5 20 Andi
1717104 Xiangshi Chen 6,7,1,2 24 Ori
1717136 Ruiwen Wang 3,4,5,6 28 Andi
1717202 Runjie Wang 7,1,2,3 20 Ori
1719406 Zhihao Liang 4,5,6,7 24 Andi
1823197 Hao Ao 1,2,3,4 28 Ori
1927553 Alijon Avliyoqulov 5,6,7,1 20 Andi
1822751 Hongyu Bao 2,3,4,5 24 Ori
1823185 Feiyu Cai 6,7,1,2 28 Andi
1824083 Mingrui Cai 3,4,5,6 20 Ori
1822768 Tianyu Cang 7,1,2,3 24 Andi
1823199 Kechang Chen 4,5,6,7 28 Ori
1822317 Muyu Chen 1,2,3,4 20 Andi
1822270 Yuyuan Chen 5,6,7,1 24 Ori
1823126 Yongqiao Chen 2,3,4,5 28 Andi
1825217 Yitong Chen 6,7,1,2 20 Ori
1823173 Zhiang Chen 3,4,5,6 24 Andi
1717587 Shihao Cheng 7,1,2,3 28 Ori
1823689 Yuxin Chu 4,5,6,7 20 Andi
1825258 Ruoxi Cui 1,2,3,4 24 Ori
1822200 Chengmurong Ding 5,6,7,1 28 Andi
1715726 Ruoxi Ding 2,3,4,5 20 Ori
1825261 Jiayu Du 6,7,1,2 24 Andi
1823190 Wenchang Du 3,4,5,6 28 Ori
1824861 Yuxin Du 7,1,2,3 20 Andi
1825271 Jiachen Duan 4,5,6,7 24 Ori
1510186 Jiaming Gao 1,2,3,4 28 Andi
1715539 Xingyu Gao 5,6,7,1 20 Ori
1822756 Xinyu Gao 2,3,4,5 24 Andi
1824124 Yutong Ge 6,7,1,2 28 Ori
1824193 Tianyu Geng 3,4,5,6 20 Andi
1825266 Yuechi Guan 7,1,2,3 24 Ori
1822760 Jiadong Guo 4,5,6,7 28 Andi
1822275 Qiuming Guo 1,2,3,4 20 Ori
1823214 Wenjun He 5,6,7,1 24 Andi
1718577 Xin He 2,3,4,5 28 Ori
1823670 Xiang He 6,7,1,2 20 Andi
1825491 Aurelia Aileen Herawan 3,4,5,6 24 Ori
1823514 Wanqin Hou 7,1,2,3 28 Andi
1823106 Jianing Hu 4,5,6,7 20 Ori
1822321 Sixian Hu 1,2,3,4 24 Andi
1824175 Shichen Huang 5,6,7,1 28 Ori
1824085 Zhenhao Huang 2,3,4,5 20 Andi
1716852 Jiayu Jian 6,7,1,2 24 Ori
1823137 Chengjun Li 3,4,5,6 28 Andi
1825290 Chenyuan Li 7,1,2,3 20 Ori
1823186 Qianjiao Li 4,5,6,7 24 Andi
1823154 Xin Li 1,2,3,4 28 Ori
1823222 Xiaoji Li 5,6,7,1 20 Andi
1715977 Yang Li 2,3,4,5 24 Ori
1821832 Yuanxi Li 6,7,1,2 28 Andi
1822276 Ziyun Li 3,4,5,6 20 Ori
1822501 Ziyu Li 7,1,2,3 24 Andi
1823179 Ziqian Li 4,5,6,7 28 Ori
1823221 Zhuohang Li 1,2,3,4 20 Andi
1825267 Haibo Lian 5,6,7,1 24 Ori
1825201 Xinran Liang 2,3,4,5 28 Andi
1823208 Keyao Liao 6,7,1,2 20 Ori
1823203 Shifeng Lin 3,4,5,6 24 Andi
1823204 Sheng Lin 7,1,2,3 28 Ori
1824205 Yukun Lin 4,5,6,7 20 Andi
1822319 Maoqing Ling 1,2,3,4 24 Ori
1614266 Huayu Liu 5,6,7,1 28 Andi
1823123 Runyu Liu 2,3,4,5 20 Ori
1824817 Ruofu Liu 6,7,1,2 24 Andi
1406089 Yuxuan Liu 3,4,5,6 28 Ori
1614272 Yifu Liu 7,1,2,3 20 Andi
1824213 Zhengjun Liu 4,5,6,7 24 Ori
1824772 Yujia Long 1,2,3,4 28 Andi
1822196 Hanzhe Lu 5,6,7,1 20 Ori
1823669 Yichen Luo 2,3,4,5 24 Andi
1824116 Yi Luo 6,7,1,2 28 Ori
1824199 Xinran Ma 3,4,5,6 20 Andi
1822795 Jingyang Min 7,1,2,3 24 Ori
1821900 Yang Ni 4,5,6,7 28 Andi
1823950 Shilong Nie 1,2,3,4 20 Ori
1821873 Xin Pan 5,6,7,1 24 Andi
1825085 Ziqing Peng 2,3,4,5 28 Ori
1822215 Chengfei Qian 6,7,1,2 20 Andi
1822300 Ziheng Qiao 3,4,5,6 24 Ori
1824185 Yushu Qin 7,1,2,3 28 Andi
1823160 Chengxin Ren 4,5,6,7 20 Ori
1822246 Guoping Ruan 1,2,3,4 24 Andi
1931542 Kelvin Septian 5,6,7,1 28 Ori
1824743 Hongji Shen 2,3,4,5 20 Andi
1612613 Xuanyu Shen 6,7,1,2 24 Ori
1822684 Yi Shen 3,4,5,6 28 Andi
1824102 Dian Sheng 7,1,2,3 20 Ori
1823671 Jichun Shi 4,5,6,7 24 Andi
1822230 Yinong Shi 1,2,3,4 28 Ori
1716601 Yidi Song 5,6,7,1 20 Andi
1509645 Ziyu Song 2,3,4,5 24 Ori
1825219 Haodong Su 6,7,1,2 28 Andi
1613801 Jiacheng Sun 3,4,5,6 20 Ori
1823169 Jiaxi Sun 7,1,2,3 24 Andi
1824220 Yu Sun 4,5,6,7 28 Ori
1822250 Rui Tan 1,2,3,4 20 Andi
1821927 Jingning Tang 5,6,7,1 24 Ori
1823500 Yuqing Tian 2,3,4,5 28 Andi
1824247 Guanxiang Tong 6,7,1,2 20 Ori
1822206 Xiangzhi Tong 3,4,5,6 24 Andi
1717352 Binfeng Wang 7,1,2,3 28 Ori
1825215 Tailai Wang 4,5,6,7 20 Andi
1717300 Xinkang Wang 1,2,3,4 24 Ori
1825235 Yihan Wang 5,6,7,1 28 Andi
1824264 Zishun Wang 2,3,4,5 20 Ori
1823517 Jinnan Wei 6,7,1,2 24 Andi
1823162 Shihang Wei 3,4,5,6 28 Ori
1825159 Wenxi Wei 7,1,2,3 20 Andi
1823195 Feiyang Weng 4,5,6,7 24 Ori
1825498 Anthony Bima Wijaya 1,2,3,4 28 Andi
1715713 Siyuan Wu 5,6,7,1 20 Ori
1822292 Yuchen Xia 2,3,4,5 24 Andi
1824107 Siyu Xing 6,7,1,2 28 Ori
1510111 Baicheng Xiong 3,4,5,6 20 Andi
1822187 Yixuan Xiong 7,1,2,3 24 Ori
1822307 Chenhao Xu 4,5,6,7 28 Andi
1824221 Yifeng Xu 1,2,3,4 20 Ori
1824821 Heming Yang 5,6,7,1 24 Andi
1716256 Sheng Yu 2,3,4,5 28 Ori
1824187 Xiaoran Yu 6,7,1,2 20 Andi
1823131 Bohao Zhang 3,4,5,6 24 Ori
1823142 Chengrui Zhang 7,1,2,3 28 Andi
1824811 Hanchen Zhang 4,5,6,7 20 Ori
1823368 Jinwei Zhang 1,2,3,4 24 Andi
1823789 Jingqun Zhang 5,6,7,1 28 Ori
1824078 Jinyuan Zhang 2,3,4,5 20 Andi
1824825 Jingtian Zhang 6,7,1,2 24 Ori
1825361 Tailong Zhang 3,4,5,6 28 Andi
1614022 Weijian Zhang 7,1,2,3 20 Ori
1825181 Wenxin Zhang 4,5,6,7 24 Andi
1823159 Xueyao Zhang 1,2,3,4 28 Ori
1824158 Xuyuan Zhang 5,6,7,1 20 Andi
1824805 Xingjian Zhang 2,3,4,5 24 Ori
1822173 Zixian Zhang 6,7,1,2 28 Andi
1822279 Zihao Zhang 3,4,5,6 20 Ori
1822778 Linghao Zhao 7,1,2,3 24 Andi
1718161 Tiange Zhao 4,5,6,7 28 Ori
1824103 Han Zheng 1,2,3,4 20 Andi
1824862 Hao Zheng 5,6,7,1 24 Ori
1822237 Xincheng Zhong 2,3,4,5 28 Andi
1823147 Yuzhou Zhong 6,7,1,2 20 Ori
1825227 Xiaoyi Zhou 3,4,5,6 24 Andi
1822759 Zeyuan Zhou 7,1,2,3 28 Ori
1613291 Hongyi Zhu 4,5,6,7 20 Andi
1825240 Hongyu Zhu 1,2,3,4 24 Ori
1822320 Kaiyue Zhu 5,6,7,1 28 Andi
1822025 Qi Zhu 2,3,4,5 20 Ori
1822194 Zhaohan Zhu 6,7,1,2 24 Andi
1825223 Zheng Zhu 3,4,5,6 28 Ori
1825711 Zhaoxi Zhu 7,1,2,3 20 Andi
1822267 Kainan Zhuang 4,5,6,7 24 Ori
1824285 Guangze Zu 1,2,3,4 28 Andi