CS代写 EEL3701C Fall 2022

College Performance Data

Digital Logic And Computing Systems

Chapter 05 – RTL Components
EEL3701C Fall 2022

DEPARTMENT OR UNIT NAME. DELETE FROM MASTER SLIDE IF N/A
Department of Electrical & Computer Engineering

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Register-Transfer Level (RTL)

Transistors
Logic Circuits
Micro Architecture
(Register-Transfer Level)
Instruction set Architecture

Complex circuit components are made from simple elements

Information flows are represented, processed, transported and stored as words in registers.

Information flow from register to register through combinational units:
 Register-Transfer

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Word (bundle)gates
Multiplexer / Demultiplexer
Encoder / Decoder
Arithmetic Circuits

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m × n memory
n bits per word
2k × n read and write memory
memory external view
Memory: basic concepts
Stores large number of bits
m x n: m words of n bits each
k = Log2(m) address input signals
or m = 2^k words
e.g., 4,096 x 8 memory:
32,768 bits
12 address input signals
8 input/output data signals

Memory access
r/w: selects read or write
enable: read or write only when asserted
multiport: multiple accesses to different locations simultaneously

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2k × n ROM
External view
ROM: “Read-Only” Memory

Nonvolatile memory
Can be read from but not written to, by a processor in an embedded system
Traditionally written to, “programmed”, before inserting to embedded system
Store software program for general-purpose processor
program instructions can be one or more ROM words
Store constant data needed by system
Implement combinational circuit

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8 × 4 ROM
3×8 decoder
programmable connection
Internal view
Example: 8 x 4 ROM

Horizontal lines = words
Vertical lines = data
Lines connected only at circles
Decoder sets word 2’s line to 1 if address input is 010
Data lines Q3 and Q1 are set to 1 because there is a “programmed” connection with word 2’s line
Word 2 is not connected with data lines Q2 and Q0
Output is 1010

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Truth table

Inputs (address) Outputs
a b c y z
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 1 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

0 0
0 1
0 1
1 0
1 0
1 1
1 1
1 1

Implementing combinational function

Any combinational circuit of n functions of same k variables can be done with 2^k x n ROM

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Mask-programmed ROM

Connections “programmed” at fabrication
set of masks
Lowest write ability
Highest storage permanence
bits never change unless damaged
Typically used for final design of high-volume systems
spread out NRE cost for a low unit cost

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OTP ROM: One-time
programmable ROM

Connections “programmed” after manufacture by user
user provides file of desired contents of ROM
file input to machine called ROM programmer
each programmable connection is a fuse
ROM programmer blows fuses where connections should not exist
Very low write ability
typically written only once and requires ROM programmer device
Very high storage permanence
bits don’t change unless reconnected to programmer and more fuses blown
Commonly used in final products
cheaper, harder to inadvertently modify

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floating gate
Erasable programmable ROM

Programmable component is a MOS transistor
Transistor has “floating” gate surrounded by an insulator
(a) Negative charges form a channel between source and drain storing a logic 1
(b) Large positive voltage at gate causes negative charges to
move out of channel and get trapped in floating gate storing a logic 0
(c) (Erase) Shining UV rays on surface of floating-gate causes negative
charges to return to channel from floating gate restoring the logic 1
(d) An EPROM package showing quartz window through which UV light can pass
Better write ability
can be erased and reprogrammed thousands of times
Reduced storage permanence
program lasts about 10 years but is susceptible to radiation and electric noise
Typically used during design development

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EEPROM: Electrically erasable programmable ROM

Programmed and erased electronically
typically by using higher than normal voltage
can program and erase individual words
Better write ability
can be in-system programmable with built-in circuit to provide higher than normal voltage
built-in memory controller commonly used to hide details from memory user
writes very slow due to erasing and programming
“busy” pin indicates to processor EEPROM still writing
can be erased and programmed tens of thousands of times
Similar storage permanence to EPROM (about 10 years)
Far more convenient than EPROMs, but more expensive

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Flash Memory

Fast erase
Large blocks of memory erased at once, rather than one word at a time
Blocks typically several thousand bytes large
Writes to single words may be slower
Entire block must be read, word updated, then entire block written back
Used with embedded systems storing large data items in nonvolatile memory
e.g., digital cameras, TV set-top boxes, cell phones
Extension of EEPROM
Same floating gate principle
Same write ability and storage permanence

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RAM (write-read memory) can be randomly written and randomly read
Inputs and Outputs
k bit address bus ABUS
n bit data bus DBUS
control signals MR (memory read) and MW (memory write)
MR=1 means that value at address location defined
by ABUS must be place on the bus (read)

MW=1 means that the value on the bus DBUS
must be stored at the location defined by ABUS

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Architecture of a (2k x n) bit RAM

Data Buffer
Memory Cells

controller

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2k × n read and write memory
external view
2×4 decoder
Memory cell
To every cell
internal view
RAM: “Random-access” memory

Typically volatile memory
bits are not held without power supply
Read and written to easily by embedded system during execution
Internal structure more complex than ROM
a word consists of several memory cells, each storing 1 bit
each input and output data line connects to each cell in
its column
rd/wr connected to every cell
when row is enabled by decoder, each cell has logic that stores
input data bit when rd/wr indicates write or outputs stored bit when
rd/wr indicates read

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RAM Simplified Architecture

Write/Read

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RAM Simplified Architecture

Write/Read

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RAM Simplified Architecture

Write/Read

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memory cell internals
Basic types of RAM

SRAM: Static RAM
Memory cell uses flip-flop to store bit
Requires 6 transistors
Holds data as long as power supplied
DRAM: Dynamic RAM
Memory cell uses MOS transistor and capacitor to store bit
More compact than SRAM
“Refresh” required due to capacitor leak
word’s cells refreshed when read
Typical refresh rate 15.625 microsec.
Slower to access than SRAM

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Important properties
Capacity: Number of bits
Organization: number of address bits k, number of data bits n
Access Time: time to read a word from or write a word in the memory

2 Types of RAM: SRAM und DRAM.
SRAMs (static RAM) have smaller capacity than DRAMs and more expensive, but better access time. The memory content is available for as longer as power is on

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Composing memory

Memory size needed often differs from size of
readily available memories
When available memory is larger, simply ignore
unneeded high-order address bits and higher
data lines
When available memory is smaller, compose several smaller memories into one larger memory
Connect side-by-side to increase width of words
Connect top to bottom to increase number of words
added high-order address line selects smaller memory containing desired word using a decoder
Combine techniques to increase number and width of words

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2m × 3n ROM
2m × n ROM
2m × n ROM
2m × n ROM
Increase width of words
Composing memory
Parallel Composition

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2m+1 × n ROM
2m × n ROM
2m × n ROM
1 × 2 decoder
Increase number of words
Composing memory
Serial composition

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Increase number and width of words
Composing memory
Hybrid Composition

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Composing memory

Briefly define each of the following: mask-programmed ROM, PROM, EPROM, EEPROM, flash EEPROM, RAM, SRAM, DRAM, PSRAM, NVRAM.
Sketch the internal design of a 4×3 ROM.
Sketch the internal design of a 4×3 RAM
Compose 1kx8 ROM’s into a 1kx32 ROM (note: 1k actually means 1028 words).
Compose 1kx8 ROM’s into an 8kx8 ROM.
Compose 1kx8 ROM’s into a 2kx16 ROM.
Show how to use a 1kx8 ROM to implement a 512×6 ROM.

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System Implementation with Memory

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A3 A2 A1 A0 CE D1 D0
X X X X 1 Z Z
0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 0 1
0 0 1 1 0 1 1
0 1 0 0 0 1 0
0 1 0 1 0 1 1
0 1 1 0 0 1 0
0 1 1 1 0 0 0
1 0 0 0 0 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 0 1 1 0 1 1
1 1 0 0 0 1 0
1 1 0 1 0 1 1
1 1 1 0 0 1 0
1 1 1 1 0 0 0
X X X X 1 Z Z
1 1 0 0 0 1 1
1 1 0 1 0 0 0
1 1 1 0 0 1 1
1 1 1 1 0 0 1
1 0 0 0 0 0 0
1 0 0 1 0 0 1
1 0 1 0 0 0 0
1 0 1 1 0 1 0
0 1 0 0 0 1 1
0 1 0 1 0 0 0
0 1 1 0 0 1 1
0 1 1 1 0 0 1
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 0
0 0 1 1 0 1 0

DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING

X X X X H Z Z
L L L L L L H
L L L H L H L
L L H L L L H
L L H H L H 1
L H L L L H L
L H L H L H H
L H H L L H L
L H H H L L L
H L H L L L H
H L L H L H L
H L H L L L H
H L H H L H H
H H L L L H L
H H L H L H L
H H H L L H L
H H H H L L L
X X X X 1 Z Z
1 1 0 0 0 1 1
1 1 0 1 0 0 0
1 1 1 0 0 1 1
1 1 1 1 0 0 1
1 0 0 0 0 0 0
1 0 0 1 0 0 1
1 0 1 0 0 0 0
1 0 1 1 0 1 0
0 1 0 0 0 1 1
0 1 0 1 0 0 0
0 1 1 0 0 1 1
0 1 1 1 0 0 1
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 0
0 0 1 1 0 1 0

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System Implementation with Memory

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(2k x n)-bit RAM

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