CS计算机代考程序代写 assembly The LC-2 Instruction Set Architecture

The LC-2 Instruction Set Architecture

Chapter 5
The LC-3

Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
5-
Instruction Set Architecture
ISA = All of the programmer-visible components
and operations of the computer
memory organization
address space — how may locations can be addressed?
addressibility — how many bits per location?
register set
how many? what size? how are they used?
instruction set
opcodes
data types
addressing modes
ISA provides all information needed for someone that wants to
write a program in machine language or assembly language
(or translate from a high-level language to machine language).

5-
LC-3 Overview: Memory and Registers
Memory
address space: 216 locations (16-bit addresses) or 64KB (65536)
addressability: 16 bits (instead of 8 bits)

Registers
temporary storage, accessed in a single machine cycle
accessing memory generally takes longer than a single cycle
eight general-purpose registers: R0 – R7
each 16 bits wide
how many bits to uniquely identify a register? (3 bits)
other registers
not directly addressable, but used by (and affected by) instructions
PC (program counter), condition codes(N, Z,P)

5-
LC-3 Overview: Instruction Set
Opcodes
15 opcodes
Operate instructions(3): ADD, AND, NOT
Data movement instructions(7): LD, LDI, LDR, LEA, ST, STR, STI
Control instructions(5): BR, JSR/JSRR, JMP, RTI, TRAP
Total 15 instructions
some opcodes set/clear condition codes, based on result:
N = negative, Z = zero, P = positive (> 0)
Data Types
16-bit 2’s complement integer
Addressing Modes
How is the location of an operand specified?
non-memory addresses: immediate, register
memory addresses: PC-relative, indirect, base+offset

5-
LC-3 Instruction Set
ADD 0 0 0 1 DR SR1 0 0 0 SR2
ADD 0 0 0 1 DR SR1 1 Imm5
AND 0 1 0 1 DR SR1 0 0 0 SR2
AND 0 1 0 1 DR SR1 1 Imm5
BR 0 0 0 0 n z p PC offset9
JMP 1 1 0 0 0 0 0 BaseR 0 0 0 0 0 0
JSR 0 1 0 0 1 PC offset11
JSRR 0 1 0 0 0 0 0 BaseR 0 0 0 0 0 0
LD 0 0 1 0 DR PC offset9
LDI 1 0 1 0 DR PC offset9
LDR 0 1 1 0 DR BaseR Offset6
LEA 1 1 1 0 DR PC offset9
NOT 1 0 0 1 DR SR 1 1 1 1 1 1
RET 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0
RTI 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ST 0 0 1 1 SR PC offset9
STI 1 0 1 1 SR PC offset9
STR 0 1 1 1 SR BaseR Offset6
TRAP 1 1 1 1 0 0 0 0 Trap vect8
reserved 1 1 0 1 x x x x x x x x x x x x

unary operator
binary operator

Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
5-
Operate Instructions
Only three operations: ADD, AND, NOT

Source and destination operands are registers
These instructions do not reference main memory.
ADD and AND can use “immediate” mode,
where one operand is hard-wired into the instruction.

Will show dataflow diagram with each instruction.
illustrates when and where data moves
to accomplish the desired operation

5-
NOT (Register)
Note: Src and Dst
could be the same register.

5-
ADD/AND (Register)
this zero means “register mode”

ADD/AND (Immediate)
Note: Immediate field is
sign-extended.
5 bits:

this one means “immediate mode”

5-
Using Operate Instructions
With only ADD, AND, NOT…
How do we subtract?

How do we OR?

How do we copy from one register to another?

How do we initialize a register to zero?

Subtract: R3 = R1 – R2
Take 2’s complement of R2, then add to R1.
(1) R2 = NOT(R2)
(2) R2 = R2 + 1
(3) R3 = R1 + R2

OR: R3 = R1 OR R2
Use DeMorgan’s Law — invert R1 and R2, AND, then invert result.
(1) R1 = NOT(R1)
(2) R2 = NOT(R2)
(3) R3 = R1 AND R2
(4) R3 = NOT(R3)

Initialize to zero: R1 = 0
R1 = R1 AND 0 (And-immediate)

5-
Using Operate Instructions
With only ADD, AND, NOT…
How do we subtract?
Negate the second number (Not and ADD 1) and then do ADD
operation

How do we OR?
NOT both operands and AND them, and then NOT again

How do we copy from one register to another?
ADD an immediate 0

How do we initialize a register to zero?
AND 0

Subtract: R3 = R1 – R2
Take 2’s complement of R2, then add to R1.
(1) R2 = NOT(R2)
(2) R2 = R2 + 1
(3) R3 = R1 + R2

OR: R3 = R1 OR R2
Use DeMorgan’s Law — invert R1 and R2, AND, then invert result.
(1) R1 = NOT(R1)
(2) R2 = NOT(R2)
(3) R3 = R1 AND R2
(4) R3 = NOT(R3)

Initialize to zero: R1 = 0
R1 = R1 AND 0 (And-immediate)

5-
Data Movement Instructions
Load — read data from memory to register
LD: PC-relative mode
LDR: base+offset mode
LDI: indirect mode
Store — write data from register to memory
ST: PC-relative mode
STR: base+offset mode
STI: indirect mode

Question: How to move data from one memory to another?

5-
Data Movement Instructions
Load effective address — compute address,
save in register
LEA: immediate mode
does not access memory
LEA 1 1 1 0 DR PC offset9

Can create any value to store in DR, such that:

5-
PC-Relative Addressing Mode
Want to specify address directly in the instruction
But an address is 16 bits, and so is an instruction!
After subtracting 4 bits for opcode
and 3 bits for register, we only have 9 bits available for address.

Solution:
Use the 9 bits as a signed offset from the current PC.

9 bits:
Can form any address X, such that:

Remember that PC is incremented as part of the FETCH phase;
This is done before the EVALUATE ADDRESS stage.

5-
ST (PC-Relative)

5-
Indirect Addressing Mode
With PC-relative mode, can only address data
within 256 words of the instruction.
What about the rest of memory?

Solution #1:
Read address from memory location,
then load/store to that address.

First address is generated from PC and IR
(just like PC-relative addressing), then the
content of that address is used as target for load/store.

sign-extended

5-
STI (Indirect)

sign-extended

5-
Base + Offset Addressing Mode
With PC-relative mode, can only address data
within 256 words of the instruction.
What about the rest of memory?

Solution #2:
Use a register to generate a full 16-bit address.

4 bits for opcode, 3 for src/dest register,
3 bits for base register — remaining 6 bits are used
as a signed offset.
Offset is sign-extended before adding to base register.

6 bits:

sign-extended

5-
STR (Base+Offset)

sign-extended

5-
Load Effective Address (LEA)
Computes address like PC-relative (PC plus signed offset) and stores the result into a register.

Note: The address is stored in the register,
not the contents of the memory location.

Example1
Address Instruction Comments
x30F6 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 R1  PC – 3 = x30F4
x30F7 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 R2  R1 + 14 = x3102
x30F8 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 M[PC – 5]  R2
M[x30F4]  x3102
x30F9 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2  0
x30FA 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 R2  R2 + 5 = 5
x30FB 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 M[R1+14]  R2
M[x3102]  5
x30FC 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 R3  M[M[x30F4]]
R3  M[x3102]
R3  5

opcode

LEA
ADD
ST
AND
ADD
STR
LDI

5-
Example1
0011000011110110
1110001111111101
0001010001101110
0011010111111011
0101010010100000
0001010010100101
0111010001001110
1010011111110111
ST
M[PC + F6]  R0
M[x30F6]  R0
PC=0x30F6, R0=0x0000
PC=0x3000
R0=1110001111111101

5-
Control Instructions
Used to alter the sequence of instructions
(by changing the Program Counter)

Conditional Branch
branch is taken if a specified condition is true
signed offset is added to PC to yield new PC
else, the branch is not taken
PC is not changed, points to the next sequential instruction
Unconditional Branch (or Jump)
always changes the PC
TRAP
changes PC to the address of an OS “service routine”
routine will return control to the next instruction (after TRAP)

5-
Condition Codes
LC-3 has three condition code registers:
N — negative
Z — zero
P — positive (greater than zero)

Set by any instruction that writes a value to a register
(ADD, AND, NOT, LD, LDR, LDI, LEA)

Exactly one will be set at all times
Based on the last instruction that altered a register

Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
5-
Branch Instruction
Branch specifies one or more condition codes.
If the set bit is specified, the branch is taken.
PC-relative addressing:
target address is made by adding signed offset (IR[8:0])
to current PC.
Note: PC has already been incremented by FETCH stage.
Note: Target must be within 256 words of BR instruction.

If the branch is not taken,
the next sequential instruction is executed.

Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
5-
BR (PC-Relative)
What happens if bits [11:9] are all zero? All one?

BR
BRn
BRz
BRp
BRnz
BRnp
BRzp
BRnzp

If all zero, no CC is tested, so branch is never taken. (See Appendix B.)
If all one, then all are tested. Since at least one of the CC bits is set to one after each operate/load instruction, then branch is always taken. (Assumes some instruction has set CC before branch instruction, otherwise undefined.)

5-
Using Branch Instructions
Compute sum of 12 integers.
Numbers start at location x3100.
Program starts at location x3000.
R1  x3100
R3  0
R2  12
R2=0?
R4  M[R1]
R3  R3+R4
R1  R1+1
R2  R2-1
NO
YES

Example2
Address Instruction Comments
x3000 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 R1  x3100 (PC+0xFF)
x3001 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 R3  0
x3002 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2  0
x3003 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 R2  12
x3004 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 If Z, goto x300A (PC+5)
x3005 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 Load next value to R4
x3006 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 Add R4 to R3
x3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 Increment R1 (pointer)
X3008 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 Decrement R2 (counter)
x3009 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 Goto x3004 (PC-6)

LEA
AND
AND
ADD
BRz
LDR
ADD
ADD
ADD
BRnzp
x300A

Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
5-
Example2
0011000000000000
1110001011111111
0101011011100000
0101010010100000
0001010010101100
0000010000000101
0110100001000000
0001011011000100
0001001001100001
0001010010111111
0000111111111010
ST
M[PC]  R0
M[x3000]  R0
PC=0x3000, R0=0x0000
PC=0x3000
R0=1110001011111111

5-
JMP (Register)
Jump is an unconditional branch — always taken.
Target address is the contents of a register.
Allows any target address.

Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
5-
TRAP
Calls a service routine, identified by 8-bit “trap vector.”

When routine is done,
PC is set to the instruction following TRAP.
(We’ll talk about how this works later.)

vector routine
x23 input a character from the keyboard
x21 output a character to the monitor
x25 halt the program

5-
Another Example
Count the occurrences of a character in a file
Program begins at location x3000
Read character from keyboard
Load each character from a “file”
File is a sequence of memory locations
Starting address of file is stored in the memory location
immediately after the program
If file character equals input character, increment counter
End of file is indicated by a special ASCII value: EOT (x04)
At the end, print the number of characters and halt
(assume there will be less than 10 occurrences of the character)

A special character used to indicate the end of a sequence
is often called a sentinel.
Useful when you don’t know ahead of time how many times
to execute a loop.

assume less than 10 occurrences of the character
What if more than 10?

Example3 (1 of 2)
Address Instruction Comments
x3000 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2  0 (counter)
x3001 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 R3  M[x3012] (ptr)
x3002 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 Input to R0 (TRAP x23)
x3003 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 R1  M[R3]
x3004 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 R4  R1 – 4 (EOT)
x3005 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 If Z, goto x300E
x3006 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 R1  NOT R1
x3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 R1  R1 + 1
X3008 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 R1  R1 + R0
x3009 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 If N or P, goto x300B

Example3(2 of 2)
Address Instruction Comments
x300A 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 R2  R2 + 1
x300B 0 0 0 1 0 1 1 0 1 1 1 0 0 0 0 1 R3  R3 + 1
x300C 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 R1  M[R3]
x300D 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 Goto x3004
x300E 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 R0  M[x3013]
x300F 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 R0  R0 + R2
x3010 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 Print R0 (TRAP x21)
x3011 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 1 HALT (TRAP x25)
X3012 Starting Address of File
0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 For example 0x3200
x3013 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 ASCII x30 (‘0’)

Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
5-
Example3
0011000000000000
0101010010100000
0010011000010000
1111000000100011
0110001011000000
0001100001111100
0000010000001000
1001001001111111
0001001001100001
0001001001000000
0000101000000001
0001010010100001
0001011011100001
0110001011000000
0000111111110110
0010000000000100
0001000000000010
1111000000100001
1111000000100101
0011001000000000
0000000000110000
ST
M[PC]  R0
M[x3000]  R0
PC=0x3000, R0=0x0000
PC=0x3000
R0=0101010010100000

5-
LC-3
Data Path
Revisited
Filled arrow
= info to be processed.
Unfilled arrow
= control signal.

5-
LC-3
Data Path
Revisited
ADD and AND
Instructions

ADD 0 0 0 1 DR SR1 0 0 0 SR2
ADD 0 0 0 1 DR SR1 1 Imm5
AND 0 1 0 1 DR SR1 0 0 0 SR2
AND 0 1 0 1 DR SR1 1 Imm5

5-
LC-3
Data Path
Revisited
NOT Instruction
NOT 1 0 0 1 DR SR 1 1 1 1 1 1

5-
LC-3
Data Path
Revisited
LD and ST
LDI and STI Instructions

LD 0 0 1 0 DR PC offset9
LDI 1 0 1 0 DR PC offset9
ST 0 0 1 1 SR PC offset9
STI 1 0 1 1 SR PC offset9

5-
LC-3
Data Path
Revisited
LDR and STR
Instructions
LDR 0 1 1 0 DR BaseR Offset6
STR 0 1 1 1 SR BaseR Offset6

5-
LC-3
Data Path
Revisited
LEA
Instructions

LEA 1 1 1 0 DR PC offset9

5-
LC-3
Data Path
Revisited
BR
Instructions
BR 0 0 0 0 n z p PC offset9

5-
LC-3
Data Path
Revisited
JSR
Instructions
JSR 0 1 0 0 1 PC offset11

5-
LC-3
Data Path
Revisited
JMP & JSRR
Instructions

JMP 1 1 0 0 0 0 0 BR 0 0 0 0 0 0
JSRR 0 1 0 0 0 0 0 BR 0 0 0 0 0 0

5-
LC-3
Data Path
Revisited
TRAP
Instruction
TRAP 1 1 1 1 0 0 0 0 Trap vect8

PC=>R7
M[Trap Vector Tbl]=>PC

5-
Data Path Components
Global bus
special set of wires that carry a 16-bit signal
to many components
inputs to the bus are “tri-state devices,”
that only place a signal on the bus when they are enabled
only one (16-bit) signal should be enabled at any time
control unit decides which signal “drives” the bus
any number of components can read the bus
register only captures bus data if it is write-enabled by the control unit

Memory
Control and data registers for memory and I/O devices
memory: MAR, MDR (also control signal for read/write)

5-
Data Path Components
ALU
Accepts inputs from register file
and from sign-extended bits from IR (immediate field).
Output goes to bus.
used by condition code logic, register file, and memory

Register File
Two read addresses (SR1, SR2), one write address (DR)
All are 3 bits
Input from bus
result of ALU operation or memory read
Two 16-bit outputs
used by ALU, PC, memory address
data for store instructions passes through ALU

5-
Data Path Components
PC and PCMUX
Three inputs to PC, controlled by PCMUX
PC+1 – FETCH stage
Address adder – BR, JMP
bus – TRAP (discussed later)

MAR and MARMUX
Two inputs to MAR, controlled by MARMUX
Address adder – LD/ST, LDR/STR
Zero-extended IR[7:0] — TRAP (discussed later)

5-
Data Path Components
Condition Code Logic
Looks at value on bus and generates N, Z, P signals
Registers set only when control unit enables them (LD.CC)
only certain instructions set the codes
(ADD, AND, NOT, LD, LDI, LDR, LEA)

Control Unit – Finite State Machine
On each machine cycle, changes control signals for next phase
of instruction processing
who drives the bus? (GatePC, GateALU, …)
which registers are write enabled? (LD.IR, LD.REG, …)
which operation should ALU perform? (ALUK)
…
Logic includes decoder for opcode, etc.

5-
Summary
What is ISA?
What is PC?
LC-3 addressing modes
non-memory addresses: immediate, register
memory addresses: PC-relative, indirect, base+offset
Condition Code Logic: N, Z, and P
Understand machine code

15
offset
16
+
£
£
–

255
PC
X
256
PC
+
£
£
–

255
offset
256
+
£
£
–

31
offset
32
+
£
£
–

Count = 0
(R2 = 0)
Ptr = 1st file character
(R3 = M[x3012])
Input char
from keybd
(TRAP x23)
Done?
(R1 ?= EOT)
Load char from file
(R1 = M[R3])
Match?
(R1 ?= R0)
Incr Count
(R2 = R2 + 1)
Load next char from file
(R3 = R3 + 1, R1 = M[R3])
Convert count to
ASCII character
(R0 = x30, R0 = R2 + R0)
Print count
(TRAP x21)
HALT
(TRAP x25)
NO
NO
YES
YES

/docProps/thumbnail.jpeg

Related Posts