Microsoft PowerPoint – 14-CS2022_p2_fourteenth_lecture_2020_2021 – Compatibility Mode
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 1
Basic Computer Architecture
Computers consist of:
Datapath
Control unit
It is designed to implement a particular instruction set.
The individual instructions are the engineering
equivalent of the mathematician’s
z=f(x,y)
OPCODE DESTINATION OPERANDS
f z x,y
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 2
Opcode – Destination -Operands
OPCODE
Selects the function
DESTINATION
Is nearly always a datapath register
OPERANDS
Usually come from datapath register
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 3
Instruction Format Examples
Register
Opcode
Destination
Register (DR)
Source
Register (SA)
Source
Register (SB)
1431 15 10 9 045
Immediate
Opcode
Destination
Register (DR)
Source
Register (SA)
Operand (OP)
1431 15 10 9 045
Jump and Branch
Opcode
Address (AD)
(Left)
Source
Register (SA)
Address (AD)
(Right)
1431 15 10 9 045
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 4
Instruction Formats
Where DR, SA SB point to
processor registers in the datapath
But Operand is itself an immediate
operand
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 5
Data and Instructions in Memory
Example for a 16 Bit processor, with 7, 3, 3, 3 bits
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 6
User View of Storage
Instruction
Memory
232 x 16
Data
Memory
232 x 16
Register
File
32 x 32
Program Counter (PC)
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 7
Memory Module [entity]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity memory is — use unsigned for memory address
Port ( address : in unsigned std_logic_vector(31 downto 0);
write_data : in std_logic_vector(31 downto 0);
MemWrite, MemRead : in std_logic;
read_data : out std_logic_vector(31 downto 0));
end memory;
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 8
Memory Module [architecture]
architecture Behavioral of memory is
— we will use the least significant 9 bit of the address – array(0 to 512)
type mem_array is array(0 to 7) of std_logic_vector(31 downto 0);
— define type, for memory arrays
begin
mem_process: process (address, write_data)
— initialize data memory, X denotes hexadecimal number
variable data_mem : mem_array := (
X”00000000″, X”00000000″, X”00000000″,X”00000000″,
X”00000000″, X”00000000″, X”00000000″,X”00000000″);
variable addr:integer
begin — the following type conversion function is in std_logic_arith
addr:=conv_integer(address(2 downto 0));
if MemWrite =’1′ then
data_mem(addr):= write_data;
elsif MemRead=’1′ then
read_data <= data_mem(addr) after 10 ns;
end if;
end process;
end Behavioral;
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 9
A Single-cycle Hardwired Control Unit
We briefly consider a system with the simplest
possible control unit.
The control unit:
Maps each OPCODE to a single datapath operation.
Instructions are fetched from an instruction
memory
This is what all present systems with separate
instruction and data code do.
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 10
Single-Cycle Computer
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 11
Branch
Instruction Bit13=1
Jump occurs
Instruction Bit13=0
Conditional Branch occurs
Bit11, Bit10 and Bit9
Select the status bit
BC Status Bit
000 C
001 N
010 V
011 Z
100 C
101 N
110 V
111 Z
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 12
Jump and Branch
PL=1
Jump or Branch, loading the PC
PL=0
PC is incremented
PL=1 JB=0
Jump
PL=1 JB=1
Conditional branch
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 13
Truth Table BIT15 – BIT13
The following operations classification
helps with the implementation of the
instruction decoder
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 14
Instruction Decoder
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 15
Single-Cycle Computer
Instruction Example
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 16
Single-cycle Problem
A single-cycle control unit cannot
implement:
more complex addressing modes
Composite functions
E.g. Multiplication
A single-cycle control unit has long worst
case delay path.
Slow clock.
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 17
Worst Case Delay
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 18
Multiple-Cycle Microprogrammed Computer
(32+1) x 32
Register
file
TB || SBTA || SA
TD || DR
(2^32) x 32
Memory
M
PC
RW
PI
PL
IR
Opcode |DR|SA|SB
1
1 + 5
1 + 5 1 + 5
CAR
5 5 5
MUX C
0 1
MUX S
7 6 5 4 3 2 1 0
Z C N Z V C 1 0
MS
3 17
MUX M
0 1
32
MC
1
17
Control Memory
(2^17) x 42
17
Function
Unit
17
IL
32
MUX D
0 1N
A
3
M
S
1
1
M
C
1
I
L
1
P
I
1
P
L
1
T
D
1
T
A
1
T
B
1
M
B
5
F
S
1
MM
1
FS
5
MD
1
MUX B
1 0
32
MB
1
32
A B
Data Out
Data In AddressB
F
Zero Fill
32
MW
32
Bus A
Bus D
1
D
1
V
1
C
1
N
1
Z
V
-
C
-
N
-
Z
2
Bus B
4
Extend 10
A
DR SA
32
1
1
Data Instructions
Data Address
32
Instruction Address
SB
1
M
D
1
R
W
1
M
M
1
M
W
1
R
V
1
R
C
1
R
N
1
R
Z
Sequence Control Datapath Control
Next Address
RV || RC || RN || RZ
Reset
4
4
1
F
L
FL
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 19
Microinstruction Format
Control Memory
(2^17) x 42
17
N
A
3
M
S
1
M
C
1
I
L
1
P
I
1
P
L
1
T
D
1
T
A
1
T
B
1
M
B
5
F
S
1
M
D
1
R
W
1
M
M
1
M
W
1
R
V
1
R
C
1
R
N
1
R
Z
Sequence Control Datapath Control
1
F
L
CSU22022, 14th Lecture, Dr. M. Manzke, Page: 20
Control Word Information for Datapath
Example, our project is different!