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CSU22022, 17th Lecture, Dr. M. Manzke, Page: 1
Microprogram Design
Use ASM from Lecture 16 to design the
Microprograms
See Symbolic/Binary Microprogram on next slide
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 2
Symbolic/Binary Microprogram
This is not our control memory but similar
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 3
Indirect Instruction ASM
R32←M[R[SA]]
R[DR]←M[R32]
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 4
Right-Shift Instruction ASM
zf IR[4:0]=0?
R32←zf IR[4:0]
IR=00000111?
R[DR]←sr R[SB]
R32←R32-1
R32=0?
0
0
1
1
10
00000111
To IF
10000111
10001000
The number of shifts
to the right n must be
the same as the SB
register that holds the
value that will be
shifted by n bits to
the right
DR = SB
and
SB = Address = n sr
SRM1
SRM2
SRM3
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 5
Hardwired Multiple-Cycle Control
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 6
Hardwired Control Unit
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 7
Pipelined (based on single-cycle)
Instruction Fetch
Decode and
Operand Fetch
Execution
Write-back
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 8
Pipelined Execution Pattern
CSU22022, 17th Lecture, Dr. M. Manzke, Page: 9
Computer Architecture and
Microprocessor Systems
(32+1) x 32
Register
file
TB || SBTA || SA
TD || DR
(2^32) x 32
Memory
M
PC
RW
PI
PL
IR
Opcode |DR|SA|SB
1
1 + 5
1 + 5 1 + 5
CAR
5 5 5
MUX C
0 1
MUX S
7 6 5 4 3 2 1 0
Z C N Z V C 1 0
MS
3 17
MUX M
0 1
32
MC
1
17
Control Memory
(2^17) x 42
17
Function
Unit
17
IL
32
MUX D
0 1N
A
3
M
S
1
1
M
C
1
I
L
1
P
I
1
P
L
1
T
D
1
T
A
1
T
B
1
M
B
5
F
S
1
MM
1
FS
5
MD
1
MUX B
1 0
32
MB
1
32
A B
Data Out
Data In AddressB
F
Zero Fill
32
MW
32
Bus A
Bus D
1
D
1
V
1
C
1
N
1
Z
V
–
C
–
N
–
Z
2
Bus B
4
Extend 10
A
DR SA
32
1
1
Data Instructions
Data Address
32
Instruction Address
SB
1
M
D
1
R
W
1
M
M
1
M
W
1
R
V
1
R
C
1
R
N
1
R
Z
Sequence Control Datapath Control
Next Address
RV || RC || RN || RZ
Reset
4
4
1
F
L
FL