CSU22022, 2nd Lecture, Dr. Manzke, Page: 1
Register Transfer
Describing large-scale processor activity.
To discuss digital systems of this scale and
level of complexity we need a number of
descriptive tools.
For example:
a) Circuit schematics highlight the circuit
components and their connectivity.
CSU22022, 2nd Lecture, Dr. Manzke, Page: 2
Transfer from R1 to R2 when K1=1
Clock
K1
R1 R2n
Datapath
Circuit Schematic
CSU22022, 2nd Lecture, Dr. Manzke, Page: 3
Timing Diagram
b) Timing diagrams highlight the detailed time sequence of
transfer between registers.
Clock
K1
R2 R2 = R1
R2 previous value R2 <- R1 The transfer R2 <-r1 occurs at the end of K1 CSU22022, 2nd Lecture, Dr. Manzke, Page: 4 State Diagram c) State diagrams highlight the modes of operation and their control When the system is synchronous we normally omit the clock specification. i.e. K1 K1.CLOCK IDLE LOAD R2<-R1 K1 K1 CSU22022, 2nd Lecture, Dr. Manzke, Page: 5 Register Transfer Specification Source Register Destination Register Operation to be applied Condition or control function under which the transfer will occur. We assume synchronous operation and omit the clock K1 : R2 <- R1 Operation Source RegisterControl Function Destination Register CSU22022, 2nd Lecture, Dr. Manzke, Page: 6 Building Register-Transfer Statements Symbol(s) Description Examples Letters and Denote Registers AR, DR, R2, IR Numerals Parentheses Denote sections R2(9), AR(2),R1(7:0) of Registers Arrow Denotes data R1<-R2 transfer IR<-DR Comma Separates simultaneous R1<-R2, R3<-AR transfers Square brackets Denote memory DR<-M[AR] addressing /* a read M[AR]<-DR /* a write CSU22022, 2nd Lecture, Dr. Manzke, Page: 7 VHDL and RTL Operation RTL VHDL Combinational = <=(concurrent) Assignment Register Transfer <=(concurrent) Addition + + Subtraction - - Bitwise AND ^ and Bitwise OR or Bitwise XOR xor Bitwise NOR ¯ not Shift left (logical) sl sll Shift right (logical) sr srl Vector/Register A(3:0) A(3 downto 0) Concatenation || & CSU22022, 2nd Lecture, Dr. Manzke, Page: 8 Micro-Operation A micro-operation is an operation which can be accomplished within a small number of gate propagation delays upon data stored in adjacent registers and memory. Those commonly encountered in digital systems divide naturally into four groups Transfer or identity micro-ops copy data, e.g. R1<-R2, DR<-M[AR] Arithmetic micro-ops provide the elements of arithmetic, e.g. R0<- R1+R2 Logic micro-0ps provide per bit opearation, e.g. R1<-R2 or R2 Shift micro-ops provide bit rotations, e.g. R1<-sr R2, R0<- rol R1 CSU22022, 2nd Lecture, Dr. Manzke, Page: 9 Arithmetic Micro-ops These are operations which can be accomplished with a full-adder, which, with carry lookahead logic, can be made to deliver a substantial result, e.g. 64-bit in just a few gate delays. CSU22022, 2nd Lecture, Dr. Manzke, Page: 10 Carry Lookahead Adder CSU22022, 2nd Lecture, Dr. Manzke, Page: 11 CLA Let R0, R1,R3 be n-bit Register and consider what can be done with an n-bit CLA (carry lookahead adder) A B n n Ci S To Register Input From Register Ouput CSU22022, 2nd Lecture, Dr. Manzke, Page: 12 Conditioned use of CLA By conditioning what arrives at A,B,Ci we can achieve: Symbolic CLA Inputs Function micro-op A B C S R0<-R1+R2 R1 + R2 + 0 Addition R0<-R1-R2 R1 + R2 + 1 Subtraction R0<-R1+1 R1 + 0…0 + 1 Increment R0<-R1-1 R1 + 1…1 + 0 Decrement R0<-R2 0…0 + R2 + 0 1’s Complement R0<-R2 0…0 + R2 + 1 2’s Complement CSU22022, 2nd Lecture, Dr. Manzke, Page: 13 Add &Sub Implementation The first two of these operations may be accomplished by the addition of an XOR gate to the B-input of each full-adder, as show on the next page. CSU22022, 2nd Lecture, Part II, Dr. Manzke, Page: 14 Adder-Subtractor Circuit