CSU22022, 6th Lecture, Dr. M. Manzke, Page: 1
Arithmetic Circuit
The arithmetic circuit may
implemented with the following
components:
Parallel Adder
Build from a cascade of full-adder circuits
The data input to the parallel adder is
manipulated in order to achieve a
number of arithmetic operations
CSU22022, 6th Lecture, Dr. M. Manzke, Page: 2
N-bit Arithmetic/Logic Unit(ALU)
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G = A + Y + Cin
Select Input
S1 S0 Y Cin=0 Cin=1
0 0 all 0’s G=A G=A+1
0 1 B G=A+B G=A+B+1
1 0 B G=A+B G=A+B+1
1 1 all 1’s G=A-1 G=A
The arithmetic micro-ops can be implemented using the
carry-in Cin and two select inputs S1 & S0, which condition
the B input to deliver Y to the full-adder computing: G =
A + Y + Cin.
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Arithmetic Circuit
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Y(S,B)
Yi = S0 Bi + S1 Bi
Thus a 2:1 MUX controlled by Bi can efficiently
generates logic function Y(S,B) is derived as:
CSU22022, 6th Lecture, Dr. M. Manzke, Page: 6
One Bit Slice
One bit slice of the Arithmetic unit on the next slide.
MUXi
FAi
Bi
Ai
S1 S2
Gi
Ci
Ci+1
0 1
S
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4-Bit Arithmetic Circuit
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Logic Circuit
Select Output
S1 S0
0 0 G = A B AND
0 1 G = A B OR
1 0 G = A B XOR
1 1 G = A NOT
The logic function are similarly selected by input S1
and S0 :
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Logic Circuit
Implemented with a 4:1 MUX
One bit slice of the logic unit.
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ALU (Arithmetic/Logic)
We next use an additional 2:1 MUX
controlled by S2 to select either the
arithmetic output bit or the logic output
bit as shown on the next slide.
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One bit slice ALU
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N-bit ALU
To construct an n-bit ALU we concatenate n-bit
slices together:
G0
B0
A0
B1
A1
Bn-1
An-1
G1
Gn-1
S0 S1 S2
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Physical Implementation
Physical schematic of an n-bit ALU
assembled from a bit slices as shown on
the previous slide.
1. Note the control signals, because they
apply to the whole word, tend to cross the
datapath.
2. This geometry results in very efficient VLSI
chip implementation.
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Adder
This adder this gives us a fast combinational ALU with the
following functionality:
Select Output
S2 S1 S0 Cin
0 0 0 0 G = A TRANSFER
0 0 0 1 G = A + 1 INCREMENT
0 0 1 0 G = A + B ADD
0 0 1 1 G = A + B +1 ADD WITH C
0 1 0 0 G = A + B A plus 1’s C.B
0 1 0 1 G = A + B +1 SUBTRACT
0 1 1 0 G = A – 1 DECREMENT
0 1 1 1 G = A TRANSFER
1 0 0 X G = A B AND
1 0 1 X G = A B OR
1 1 0 X G = A B XOR
1 1 1 X G = A NOT
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4-Bit SR/SL Shifter Unit
For speed of execution the shifter unit is always implemented as
a combinational circuit based on a MUX: