Microsoft PowerPoint – Week5_Ex.pptx
Multilevel Cache Organization
1. No Cache
CPU
Main
Memory
• The CPU directly communicates with the Main Memory and no Cache
memories are involved.
• The CPU needs to access the Main Memory multiple times to access the
desired information.
2. Cache
CacheCPU
Main
Memory
• The CPU at first checks whether the desired data is present in Cache.
• If the data is present in Cache, then there is a “hit”.
• If the data is not present in Cache, then there is a “miss”.
=
• Suppose there are 8 “misses” in Cache, then the Main Memory will be accessed 8 times.
• Miss Penalty – the extra time required to bring the data into Cache from the Main Memory.
3. Multi Level Cache
Cache
L2
CPU
Main
Memory
Cache
L1
• Suppose there is 8 miss in the L1 Cache Memory and out of these 8 “misses” there is 2
miss in the L2 Cache Memory, then the Main Memory will be accessed only 2 times.
the miss penalty will be reduced considerably.
the performance of the Cache Memory will be improved.
Avg. memory access time = L1_hit * T1 + L1_miss* (T1+T2)
Miss Penalty
A
B
2 points (H,t): A (0, T1+T2)
B (1, T1)
Linear equation of [AB] line is: t = aH +b
1. H = 0 => T1 + T2 = a*0 + b => b = T1 + T2
2. H = 1 => T1 = a*1 + b = a + b
a + T1 + T2 = T1
a = -T2
t = -T2 * H + T1 + T2
t = T2 * (1-H) + T1
t = 1 μs * (1-0.95) + 0.1 μs = 0.15 μs
T1 = 0.1 μs – access time to L1 (cache)
T2 = 1 μs – access time to L2 (main memory)
H = 0.95 – hit rate
Using the graph
Cache
L2
CPU
Main
Memory
Cache
L1
H1, T1 H2, T2 TM
Consider a processor with 2 levels of Cache, L1 & L2. L1 has a hit rate of 90% and access
time of 1 ns. L2 has a hit rate of 95% and an access time of 10 ns. Main memory has an
access time of 100 ns. What is the average access time in this system?
𝑎𝑣𝑔
𝑎𝑣𝑔
• 𝑎𝑣𝑔 1 1 1 2 1 2 2 1 2 𝑀 ]
Miss penalty L1
Miss penalty L2
• 𝑎𝑣𝑔 1 1 2 1 2 𝑀