CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 1
RT Description of the Datapath
RW: R[DA] If MD then
FS(R[AA], if MB then R[BA]
else Constant in)
else DATA in,
V Cn Cn-1,
C Cn,
Z Rn-1,Rn-2,…,R0,
N Rn-1,
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 2
Symbolic Notation for Micro-ops
Because human beings working in binary
code tend to be highly error-prone, we
usually employ intuitive symbols to specify
datapath micro-ops.
Typical symbol/code assignments are:
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 3
Symbol-binary Map of
Control Word Fields
DA, AA, BA MB FS
Function Code Function Code Function Code
R0 00000 Register 0 G = A 00000
R1 00001 Constant 1 G = A + 1 00001
R2 00010 G = A + B 00010
R3 00011 MD G = A + B +1 00011
R4 00100 Function Code G = A + B 00100
R5 00101 Function 0 G = A + B +1 00101
R6 00110 Data In 1 G = A – 1 00110
R7
11111
G = A 00111
RW G = A B 01000
Function Code G = A B 01010
No Write 0 G = A B 01100
Write 1 G = A 01110
G = B 10000
G = sr B 10100
G = sl B 11000
R0
R31
00111
continue
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 4
Symbol Conversion
Field : DA AA BA MB FS MD RW
Symbol: R1 R2 R3 Register F=A+B+1 Function Write
Binary: 001 010 011 0 00101 0 1
With the symbolic notation it is easy to
accurately specify control words which may
then be automatically converted to binary.
For example: R1R2 + R3 +1
8 Register Example
CS2022 ,8th Lecture, Dr. M. Manzke, Page: 5
Microoperations Example
DIY – Convert these to binary and check your
results against the table on the next slide.
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 6
Binary Control Words from Example
8 Register Example
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 7
Examine the
figure:
Register
transfer on
Clock .
R0 – R7 are
initialised to
Rii.
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 8
Status Bits
Status bits shows the input for the Zero,
Negative, Carry-out and Overflow bits
respectively.
Hence the change following a control word
change.
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 9
Datapath Timing
The total, worst case propagation delay
determines the maximum rate at which we
may clock a system.
Q
tr R
D
tp
Combinational logic
with delay tp
T
Register with
delay tr
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 10
Timing
For successful operations we must have:
Q
tr R
D
tp
T
T tp + tr
Tmin = tp + tr
fmax = 1 / Tmin
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 11
Conventional and Timing
tr = 1ns
tp = 3+1+4+1+2ns
= 11ns
Tmin = 12ns
fmax = 1 / Tmin
= 83.3MHz
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 12
Three-Stage Pipeline
To speed things up we
can introduce register
into the combinational
logic.
Q
tr R
D
Tp/3TP
Q
tr P1
D
Tp/3
Q
tr P2
D
Tp/3
TP tp/3 + tr
Tmax = 1+4ns
fmax = 1 / Tmax
=200MHz
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 13
When a datapath is pipelined it divides
naturally into stages seen on the next
slide.
OF = Operand Fetch
EX = Execute
WB = Write Back
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 14
Schematic
CSU22022 ,8th Lecture, Dr. M. Manzke, Page: 16
Pipe Execution Pattern