PowerPoint Presentation
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Computer Systems
Week 2 (part 2)
Instructions, Assembly Language, and
Machine Code
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Lecture Objectives
To develop fundmental understading of computer
architecture & organisation, instruction sets and
assembly language programming.
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Lecture Outline
The von
CPU Cycles and Instruction Pipelining
The Harvard Architecture
Case Study – MIPS R4000
Structure
Key Features
Assembly Languages
Instruction Sets
MIPS Instruction Types
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The von (1/4)
Source: https://www.mpoweruk.com/computer_architecture.htm
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The von (2/4)
The Central Processing Unit (CPU)
The CPU consists of:
Control Unit
Arithmetic and Logical Unit (ALU)
Registers
Program Counter – Address of the Next Instruction
Instruction Register – Instruction currently being executed or decoded
Address Register – Either stores the memory address from which data
will be fetched, or the address to which data will be sent and stored
Accumulator (Register) – short-term, intermediate storage of
arithmetic and logic data computations
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The von (3/4)
System Bus
Control Bus – carries commands
from the CPU and returns status
signals from the devices
Data Bus – carries the actual data
being processed
Address Bus – carries memory
addresses from the processor to other
components
Memory (RAM)
Input / Output Units
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The von (4/4)
Clock Cycle
A signal that oscillates between
high and low – used to synchronise
(coordinate) actions.
The number of cycles that a CPU
uses per second is used to
determine its speed.
This is measured in megahertz
(MHz) and gigahertz (GHz)
The rate of the Fetch/Execute
Cycle is determined by the
computer’s clock.
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One Cycle per Clock Tick
A computer with a 1 GHz clock has one billionth of a
second—one nanosecond—between clock ticks to run the
Fetch/Execute Cycle.
Modern computers try to start an instruction on each
clock tick.
They pass off completing the instruction to other circuitry.
This process is called pipelining and frees the fetch unit to
start the next instruction before the last one is done.
It is not quite true that 1,000 instructions are executed in 1,000 ticks
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Schematic Fetch/Execute Cycle (Pipelining)
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The Harvard Architecture
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Comparison – von Neumann vs Harvard
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Case Study – MIPS R4000
Similar to von Neumann but separate interfaces to
instructions and data.
Modified Harvard architecture
CPU – top view
SGI Onyx
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Case Study – MIPS R4000
First 64-bit architecture
Integrated caches (on-chip, off-chip secondary cache)
Integrated Floating Point Unit (FPU)
Implemented in 1992
● Deep pipeline
● 1.4M transistors
● Initially 100 MHz (>50 MIPs)
Simple, well-behaved programming model
Compact set of instructions with regular format (MIPS III)
“Easy” to translate from high-level code to machine
language
Comparison:
http://www.alexvoica.com/wp-content/uploads/2015/
09/great-mips-chips-past_f.png
http://www.alexvoica.com/wp-content/uploads/2015/09/great-mips-chips-past_f.png
http://www.alexvoica.com/wp-content/uploads/2015/09/great-mips-chips-past_f.png
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Typical MIPS Pipeline
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MIPS R4000 Pipeline
8 stage pipeline (super-pipelined)
Extend IF and MEM stages to account for cache
overheads
● Split into “First” and “Second” stages followed by a “Tag Check” for
misses
● The IF tag check is done in the RF stage
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MIPS R4000 Pipeline Stages
1) IF : First half of instruction fetch; PC selection actually happens here,
together with initiation of instruction cache access
2) IS : Second half of instruction fetch, complete instruction cache
access.
3) RF : Instruction decode and register fetch, hazard checking, and also
instruction cache hit detection
4) EX : Execution, which includes effective address calculation, ALU
operation, and branch target completion of data cache access
5) DF : Data fetch, first half of data cache access
6) DS : Second half of data fetch, completion of data cache access
7) TC : Tag check, determine whether the data cache access hit
8) WB : Write back for loads and register-register operations
Source: https://www.cs.umd.edu/~meesh/cmsc411/website/proj01/MIPS4000/
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MIPS R4000 Pipeline Stages
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MIPS R4000 – Key Features
Program counter, instruction register, control unit, FPU.
32 x 32-bit / 64-bit registers, denoted $0-$31 (or r0-r31)
CPU registers can be either 32 bits or 64 bits wide,
depending on the R4000 processor mode of operation.
● $0 (r0) always stores 000…000
● $31 (r31) is the link register used by Jump and Link instructions. It
should not be used by other instructions.
Arithmetic and Logic unit
● Takes input from up to two registers
● Sends output to registers only
● One exception: also used to calculate memory addresses
Note: In the remainder of lecture, we will talk about 32-bit
registers only and denote them using $ notation.
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Assembly Language
The binary object (strings of 0’s & 1’s) file is the only
form a computer can be given software.
Computers can be programmed to translate software
expressed in other forms into binary object code.
● This process includes assembling.
Assembly language is an alternative form of machine
language that uses letters and normal numbers so
people can understand it
1) Computer scans assembly code
2) As it encounters words it looks them up in a table to convert to
binary
3) Converts numbers to binary, then assembles the binary pieces into
an instruction
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Programming Languages
Most modern software is written in a high-level
programming language
High-level languages are compiled (translated) into
assembly language, which is then assembled into binary
These languages are preferred because they have
special statement forms that help programmers describe
the complicated tasks they want done.
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Instruction Sets
Computers do not understand Java by themselves
● Several layers of software between your code and the machine itself
Java: machine independent high-level language
● Runs on anything with a JVM
● Language has many sophisticated features
● Can do complex things with little code
Machine Level: programs composed of complex
combinations of simple “instructions”
Each machine has a unique “instruction set” also
known as ISA (Instruction Set Architecture)
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Instruction Sets
The instruction set is what the programmer “sees” and
“uses”
Set of operations that the CPU can execute
Each MIPS instruction has 32-bit representation
● Binary representation – machine code
● Human readable assembly language
High-level program, describe “what” and “how”
Low-level program, also specify “where”
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MIPS Assembly Language program for n!
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MIPS Instructions
https://course.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=mips_r4000_users_manual.pdf
https://course.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=mips_r4000_users_manual.pdf
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Very Simple Example
How to add two numbers?
In Java: a = b + c;
In MIPS assembly language, need to know:
● Where is b?
● Where is c?
● Where to put the result (where is a)?
● What instruction(s) should be used?
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Very Simple Example
a = b + c
We need to
● Put b and c into the registers
● Load them from the memory
● Add them together
● The result will go into a register
● Put the result into the memory location of a
Store it
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Very Simple Example
a = b + c
Load b: lw $8, &b
Load c: lw $9, &c
Add: add $10, $8, $9
Store as a: sw $10, &a
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Another Example
a = b + c – d
Load b: lw $8, &b
Load c: lw $9, &c
Load d: lw $10, &d
Add: add $11, $8, $9
Sub: sub $11, $11, $10
Store as a: sw $11, &a
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A Bit More Complex Example
if (a == 1) b = 0;
else b = 1;
Load a: lw $8, &a
Value 1: li $9, 1
If a != 1: bne $8, $9, L1
b = 0: li $10, 0
jump: j L2
b = 1: L1: li $10, 1
End: L2: sw $10, &b
Some instructions use one register, some use
two, some use three, some take values, some
take addresses. How?
Branch Not Equal
(BNE)
If $8 != $9, jump to
instruction from
label L1
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MIPS Instruction Types
Immediate
Register
Jump
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A For Loop
y=0;
for (i=1; i<=x; i++) {
y = y + i;
}
How can we write this in MIPS Assembly ?
Hint: bgt
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li $8, 0
li $9, 1
lw $10, &x
L1:
bgt $9, $10, exit
add $8, $8, $9
addi $9, $9, 1
j L1
exit:
Solution y=0;
for (i=1; i<=x; i++) {
y = y + i;
}
y
i
x
If i>x, jump to exit
i++
y = y + i
jump back to L1 (loop)
nothing to store
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Summary
We have revisited the von and
compared it with Harvard Architecture.
We have been introduced to pipelined execution of
instructions.
We’ve also seen some detail on MIPS R4000 and
programmed it in its own language
Examples of constructing “useful” programs at the
machine level, as you learn to program in Java,
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