Input/Output: Polling and Interrupts
• I/OBackground • Polling
• Interrupts
Outline
Anatomy: 5 components of any Computer
Computer
Keyboard, Mouse Disk
(where programs, data live when not running)
Display, Printer
Processor
(active)
Control
(“brain”)
Datapath
(“brawn”)
Memory
(passive)
(where programs, data live when running)
Devices
Input Output
Motivation for Input/Output
• I/Oishowhumansinteractwithcomputers • I/O gives computers long-term memory
• I/Oletscomputersdoamazingthings
I/O Device Examples and Speeds
• Kilobytes transferred per second from mouse to display… million to one range of rates!
Device
Behaviour
Partner
Data Rate KB/s
Keyboard
Input
Human
0.01
Mouse
Input
Human
0.02
Voice output
Output
Human
5.00
Floppy disk
Storage
Machine
50.00
Laser Printer
Output
Human
100.00
Magnetic Disk
Storage
Machine
10,000.00
Network-LAN
Input/Output
Machine
10,000.00
Graphics Display
Output
Human
30,000.00
I/O Devices
• An IO device has its own registers – e.g., data, status, and control
Instruction Set Architecture for I/O
• What must the processor do for I/O?
– Input: reads a sequence of bytes
– Output: writes a sequence of bytes
– Different processors have its own I/O instructions
• Two general approaches – Memory mapped I/O
– Interrupt
Memory Mapped I/O
address 0x0000 0000
Memory Mapped I/O
control reg.
data reg.
0xFFFF0000 0xFFFFFFFF
Certain addresses are mapped to the registers of the I/O devices
address 0x0000 0000
Memory Mapped I/O
0xFFFF0000 0xFFFFFFFF
control reg.
data reg.
Use loads for input, stores for output
Processor-I/O Speed Mismatch
• Keyboard input rate is likely to be a few characters per second (limited by the user’s speed)
• The rate of output on the monitor is likely to be much faster
• Theprocessorcanexecutebillionsofinstructionspersecond. Much faster than I/O
Processor-I/O Speed Mismatch
• 1 GHz microprocessor can execute 1 billion load or store instructions per second, or 4 GB/s data rate
– I/O devices data rates range from 0.01 KB/s to 30 MB/s
• Input: device may not be ready to send data as fast as the
processor loads it
– Also, might be waiting for human to act
• Output: device not be ready to accept data as fast as processor stores it
• What to do?
Polling
Processor Checks Status before Acting
• Device generally has 2 registers:
– Control Register, is it ready to read/write? (1: ready. 0: not ready) – Data Register, contains data
• Processor reads from Control Register in loop, waiting for the Ready bit in Control register (0 becomes 1)
• Processor loads from (input) or writes to (output) data register
– Load from or Store into Data Register resets Ready bit of Control Register from 1 to 0
I/O Simulation
• MARS(anditsSPIM)cansimulateoneI/Odevice: – Memory-mapped terminal (keyboard + display)
– Read from keyboard (receiver); 2 device registers
– Writes to terminal (transmitter); 2 device registers
Receiver Control
0xffff0000
Receiver Data
0xffff0004
Transmitter Control
0xffff0008
Transmitter Data
0xffff000c
(IE)
Unused (00…00)
Unused (00…00)
Received Byte
Unused (00…00)
Unused
Transmitted Byte
Ready Ready (I.E.) (I.E.)
I/O Control and Data Registers • Control register rightmost bit (0): Ready
– Receiver: Ready==1 means character in Data Register has not yet been read; the 1 changes to 0 when data is read from Data Register
– Transmitter: Ready==1 means transmitter is ready to accept a new character; 0 means the transmitter is still busy writing last char
• For MARS, data register rightmost byte has data
– Receiver: last char from keyboard; other bytes in word are zero
– Transmitter: when we write the rightmost byte, this will write the char to the display
• In MARS, the keyboard input has – Control register 0xFFFF 0000
– Data register 0xFFFF 0004
• Input: Read from keyboard into $v0
lui $t0, 0xffff Waitloop: lw $t1, 0($t0)
# memory address 0xffff0000 # receiver control
# check ready bit with mask
I/O Example
andi $t1,$t1,0x0001
beq $t1,$zero, Waitloop
lw $v0, 4($t0) # data
• In MARS, the terminal output has – Control register 0xFFFF 0008
– Data register 0xFFFF 000C
• Output: Write to display from $a0
lui $t0, 0xffff Waitloop: lw $t1, 8($t0)
# memory address 0xffff0000 # transmitter control
# check ready bit with mask
I/O Example
andi $t1,$t1,0x0001
beq $t1,$zero, Waitloop
sw $a0, 12($t0) # data
What is the alternative to polling?
• Wasteful to have processor spend most of its time “spin- waiting” for I/O to be ready
• Wantanunplannedprocedurecallthatwouldbeinvokedonly when I/O device is ready
• Solution: use exception mechanism to help I/O by Interrupting the program when I/O ready, return when done with data transfer
I/O Interrupt
I/O Interrupt
Exception: something “out of the ordinary”
• Interrupt:
– asynchronous exception – e.g., I/O device
• Trap:
– synchronous exception – e.g., segmentation fault
I/O Interrupt
• AnI/Ointerruptislikeoverflowexceptionsexceptthat
– An I/O interrupt can happen at anytime
– It is not associated with any instruction, but it can happen in the middle of any given instruction
– It does not prevent any instruction from completion
Interrupt Driven Data Transfer
Memory
add
sub
and
or
read
store
…
jr
(1) I/O interrupt
(2) save PC
(3) jump to interrupt service routine
(4) perform transfer
user program
(5) branch back
interrupt service routine
Interrupt Driven Data Transfer • Where to save the return address for PC
• Where to go when interrupt occurs? – MIPS defines location: 0x80000180
• Howdoweknowthecauseofinterrupt?
MIPS coprocessor 0
• MIPS architecture for interrupts called coprocessor 0
• Coprocessor0hasitsown registers
MIPS coprocessor 0
• Coprocessor0Instructions – Data transfer: lwc0, swc0
– Move: mfc0, mtc0
• Coprocessor0hasitsownregisters:
Name
Number
Usage
Status
$12
Interrupt enable
Cause
$13
Exception type
EPC
$14
Return address
Interrupt Driven I/O Simulation
• Interruptenable(I.E.)
– 0: device is not allowed to have interrupt – 1: device is allowed to have interrupt
Receiver Control
0xffff0000
Receiver Data
0xffff0004
Transmitter Control
0xffff0008
Transmitter Data
(IE)
Unused (00…00)
Unused (00…00)
Received Byte
Unused (00…00)
Unused
Transmitted Byte
0xffff000c
Ready Ready (I.E.) (I.E.)
Questions Raised about Interrupts • Which I/O device caused exception?
– Needs to convey the identity of the device generating the interrupt • Canavoidinterruptsduringtheinterruptroutine?
– What if more important interrupt occurs while servicing this interrupt?
– Allow interrupt routine to be entered again?
• Who keeps track of status of all the devices, handle errors, know where to put/supply the I/O data?
The Answer is Operating Systems
• Low-levelcontrolofI/Odeviceiscomplexbecauserequires managing a set of concurrent events
• I/Osystemsoftenuseinterruptstocommunicateinformation about I/O operations
• Would like I/O services for all user programs under safe control
• You will learn this in COMP 310
Review and More Information
• Because of the speed of the processor, it must synchronize with I/O devices before using them (reading or writing)
– Polling works, but expensive
– Interrupts work, but are more complex (~100 lines of assebmly)
• References
– Textbook 5th edition A7 and A8