7611ICT Computer Systems and Networks Assessment 4 (Logisim and report) – Trimester 1, 2022
Due Date: 11:59pm Friday 20 May 2022
Software requirement:
You must use the Logisim simulator Version 2.7.1 to create your circuits. Assignments submitted using other programs will NOT BE ABLE TO BE MARKED due to incompatible file formats.
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Submission instructions:
You will be required to submit two files electronically using the Learning @ Griffith assessment 4 submission point. The two files will include only a digital logic simulator circuit (created using the Logisim simulator) for Parts A and B, and a pdf report document for Part C.
You are to submit these files electronically to the Learning @ Griffith site for this course using the assessment 4 submission point.
Important:
Filenames for your files must be prefixed with your student number, an underscore character, first name, an underscore character, last name, underscore character and then the name of the file. PLEASE DO NOT SUBMIT ZIP (or other) ARCHIVES as they may not be able to be marked.
Your Logisim file would be named:
s123456_FirstName_LastName_Logic_Circuit.circ
Your PDF report file would be named:
s123456_FirstName_LastName_Report.pdf
Files with a filename that does not adhere to this requirement may NOT be
marked or may attract a mark penalty.
Please do not submit more than 2 files as additional files may not be able to be marked.
7611ICT Computer Systems and Networks
Assessment 4 (Logisim and report) – Trimester 1, 2022 Individual Assessment
This is an individual assignment. All work submitted must be your own work. As per the warning given in the first lecture, be careful not to use the work of others as your own nor have others use your work as their own. The assessment will be marked out of 100. Marks will be allocated according to the following table:
Part A: Logisim Circuit
Part B: Logisim Circuit
Part A and B: Use of templates/subcircuits Part A and B: Labelling, Neatness
Part C: Report for Logisim
Part C: Interview
Maximum mark
40 marks 25 marks 3 marks
2 marks 10 marks 20 marks 100 marks
You are to build the following digital logic circuit in the Logisim simulator.
Task Description: Logisim Part A and Part B
Labelling, neatness, and wiring (2 marks):
You must label each circuit and template that you construct with the Logisim Annotation tool and ensure that all the inputs are labelled as instructed in this sheet. Each circuit page and subcircuit/template must be labelled with:
1. Yourname
2. Yourstudentnumber
3. Anappropriatelabelforeachinput
4. Anappropriatelabelforeachoutput
5. Anappropriatelabelforeachsubcircuit/template
Templates/Subcircuits (3 marks):
You must use templates (Logisim calls these subcircuits) to simplify the overall circuit design. Instructions for using templates/subcircuits are available on learning @ Griffith in the assessment 4 folder where you downloaded this assignment.
Note that when you create the template/subcircuit you must keep them within your single circuit file. Templates that are linked as separate files may not be able to be marked. To create a new template/subcircuit within your current file use the Project menu and the Add Circuit menu item only.
7611ICT Computer Systems and Networks Assessment 4 (Logisim and report) – Trimester 1, 2022
You will need to test various possible combinations for the inputs P1, P2, P3, Q1, Q2 and Q3 and check if the desired output is obtained for Part A. You do not need to submit your tests.
For Part B, you will also need to test the circuit to confirm that it functions correctly as per the requirements. You do not need to submit your tests.
Requirements:
For this assignment you must implement a simulation of a simple game that does not use any arithmetic computation circuitry such as adder or subtraction circuits.
The simulation has two inputs. Input 1 (P) represents the first input to the computation. P has values ranging from 0-7. Input 2 (Q) represents the second input to the computation, also with values ranging from 0-7. The computation will evaluate the following:
If P = Q-2, P equals Q-1, P = Q+1, or P = Q+ 2, the output of the Part A circuit will be successful with an output value of 1.
For any other combination of P and Q, the output of the Part A circuit will be unsuccessful with an output value of 0.
1. P=0,Q=0:PdoesnotequalQ-2,PdoesnotequalQ-1,
P does not equal Q+1, and P does not equal Q+ 2. This combination is unsuccessful.
2. P=0, Q=1:
3. P=0, Q=2:
4. P=3, Q=2:
5. P=7, Q=2:
P equals Q-1. This combination is successful. P equals Q-2. This combination is successful. P equals Q+1. This combination is successful. P does not equal Q-2, P does not equal Q-1,
P does not equal Q+1, and P does not equal Q+ 2.
This combination is unsuccessful.
6. P=3, Q=6: P does not equal Q-2, P does not equal Q-1,
P does not equal Q+1, and P does not equal Q+ 2. This combination is unsuccessful.
Note: The examples on this page represent only some selected cases. There are (many) more cases that result in successful or unsuccessful combinations. Your circuit must correctly show a successful or unsuccessful combination for each possible case.
7611ICT Computer Systems and Networks Assessment 4 (Logisim and report) – Trimester 1, 2022
Representing P and Q values:
Input Value 1 (P) will be represented by three inputs (3 bits). The three P inputs are named P1, P2, and P3. The table below shows the assignment of bits to each P value for P1, P2, and P3. Note the order of these bits, P1 is the Most Significant Bit (MSB) on the left.
Input Value 2 (Q) will be represented by three inputs (3 bits). The three Q inputs are named Q1, Q2, and Q3. The table below shows the assignment of bits to each Q value for Q1, Q2, and Q3. Note the order of these bits, Q1 is the Most Significant Bit (MSB) on the left.
000 001 010 011 100 101 110 111
Part A (40 marks):
The implementation for this part must use only the three basic logic gates (AND, OR, NOT). Each AND gate and each OR gate can have only 2 inputs. More than 2 inputs for AND and OR gates is not permitted. Each NOT gate can have only 1 input. No other logic gates or circuits are permitted to be used in your circuit for Part A.
You are required to implement a circuit where the user (you) can input a number for Input 1 (P) using value (P1, P2, and P3) and Input 2 (Q) using value (Q1, Q2, and Q3) and the circuit decodes the P1, P2, P3 and Q1, Q2, Q3 values using a decoder (see lecture notes) made up of only the permitted logic gates. The output of the decoders is used to determine if the combination is successful or unsuccessful based on the rules outlined in the requirements section on page 3. Note that because of the decoding process you do not need and must not use an adder or other arithmetic circuit to check for successful or unsuccessful outcomes.
The output of the circuit is via a single output pin (green circle in Logisim):
The output pin must be labelled Successful which is lit only if the output is successful (1). The output pin is not lit for any P and Q combinations that are unsuccessful (0).
P value P1 P2 P3
0 1 2 3 4 5 6 7
000 001 010 011 100 101 110 111
1 2 3 4 5 6 7
7611ICT Computer Systems and Networks
Assessment 4 (Logisim and report) – Trimester 1, 2022 Part B (25 marks):
For this part, the simulation will count how many unsuccessful and successful combinations have been made. As long as the number of successful P and Q combinations is less than 6 then the simulation continues, and new P and Q values can be entered and counted.
However, If the number of successful P and Q combinations becomes 6, then the simulation must stop and no changes to the output of the circuit will be permitted after this happens. Note that in this instance you can still change the P and Q values using their inputs, but this should not affect the output of the circuit.
One complication for the circuit is that when 3 unsuccessful combinations are made, the count of the number of unsuccessful combinations and successful combinations resets to 0.
In that case there are no longer any unsuccessful combinations, 6 more successful combinations would be needed to stop the simulation, and 3 more unsuccessful combinations would be needed to reset the unsuccessful and successful combinations.
Note that the reset can happen multiple times during the simulation and each time the unsuccessful count reaches 3 it would reset the successful and unsuccessful count. Also note that the 3 unsuccessful counts do not need to be consecutive. It is possible to count 1 unsuccessful, 1 or more successful, then a second unsuccessful, then 1 or more successful, and then a third unsuccessful and trigger the reset.
Using the same circuit as Part A to determine if a combination is successful, add additional circuitry to count how many unsuccessful have been tried and implement the Part B requirement above.
Note: You may need to add some wiring to your Part A solution to access the P1, P2, and P3 values in the Part B section of the circuit. However, the logic of your Part A circuit should not change, and it must still meet the requirements for Part A.
Simulation stopping condition (simulation output cannot change):
If the number of successful combinations becomes equal to 6 then an output pin labelled “Simulation Stopped” is lit, and the circuit is permanently locked. No matter the changes to inputs after this happens, the “Simulation Stopped” output pin will remain lit and cannot be turned off.
Note: The ‘Simulation Stopped’ output pin will be off unless the simulation stopping condition above is met.
7611ICT Computer Systems and Networks
Assessment 4 (Logisim and report) – Trimester 1, 2022 Part B Implementation Requirements
For Part B you may use only the following:
• The three basic logic gates (AND, OR, NOT). Each AND gate and
each OR gate can have only 2 inputs. More than 2 inputs for AND and
OR gates is not permitted. Each NOT gate can have only 1 input.
• The counter (3 bit, no wrap around) circuit from the Logisim circuit library.
• The comparator (3 bit, unsigned) circuit from the Logisim circuit library.
• The DFLIP-FLOP circuit from the Logisim circuit library. The prebuilt
DFLIP-FLOP circuit can be used to ‘remember’ some information.
• Buttons and Constants.
For Part B you will need to add a button that is pressed by you after the P and Q inputs have been entered. This is to avoid counting while you are adjusting the input pins for the P and Q input pins (P1, P2, P3, Q1, Q2, and Q3).
Template/Subcircuit requirement:
You are required to create a working and connected template/subcircuit for the following components:
• Each decoder
• The part of the circuit that determines the successful and unsuccessful
outcomes for P and Q inputs
• The whole of Part A for connecting into the Part B circuit
7611ICT Computer Systems and Networks
Assessment 4 (Logisim and report) – Trimester 1, 2022 Part C (30 marks): Report and interview
Interview (20 marks):
You will be asked to clearly demonstrate your understanding of your circuit and of its operation to your workshop demonstrator.
Interview requirement: Online students
In the interview you will be required to share your screen, turn on your camera, and use a microphone to communicate with your workshop demonstrator. You will also be required to complete a booking for the interview during week 11 and 12. More information will be made available about the process closer to week 11.
Interview requirement: On-campus students
You will complete an in-person interview during your normal week 11 and/or 12 workshop time. More information will be made available about the process closer to week 11.
Report (10 marks):
Your report 2 pages maximum must contain the following sections:
1. Yourdetails:Nameandstudentnumber 2. Screenshotsofyourcircuitdiagrams:
1. A screenshot of your whole circuit including both Part A and Part B. This screenshot the overall circuit and may also show subcircuits/templates. If you have not completed Part B then only submit what you have completed.
2. A screenshot of your Part A circuit that shows the decoder and the P and Q combination logic sections. This screenshot may include subcircuits/templates.
3. Ascreenshotoftheinnercircuitryofoneofyourdecoders.Theinner circuitry refers to the actual logic gates and not the subcircuit/template drawing.
4. AscreenshotoftheinnercircuitryofyourPandQcombinationlogic. The inner circuitry refers to the actual logic gates and not the subcircuit/template drawing.
If you have broken your P and Q combination logic up into smaller subcircuits show the inner circuitry for these also.
3. CircuitFunction:Abrief(maximum300word)descriptionofyourcircuit describing concisely and correctly in your own words how the circuit operates.
Note: Submissions with more than 2 pages, illegible screenshots, and/or more than 300 words for the description may not receive the full marks available.
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