AUSTRALIAN NATIONAL UNIVERSITY Research School of Engineering
ENGN 1218 Introduction to Electronics Week 10 Problems with Solutions: Clipper Circuits
Consider the circuit shown in Figure 1. Assume ideal diode model, R1 = 1 kΩ and RL = 15 kΩ. (a) Determine the output waveform vL(t).
(b) Sketch the output voltage waveform vL(t).
vin(t) (V) 10
Figure 1: The circuit for Question 1.
Consider the circuit shown in Figure 2. Assume Si diode model and R1 = 2 kΩ and RL = 1 kΩ. (a) Determine the output waveform vL(t).
(b) Sketch the output voltage waveform vL(t).
vin(t) (V)
Q3 (challenge problem)
Figure 2: The circuit for Question 2.
Consider the circuit shown in Figure 3. Assume Si diode model and RL ≥ 10R1. (a) Determine the output waveform vL(t).
(b) Sketch the output voltage waveform vL(t).
vin(t) (V) 10
RL vL(t) 3V
Week 10 Problems
Figure 3: The circuit for Question 3.
ANU ENGN 1218
Q4 Clamper Circuit (non-assessable problem)
Consider the circuit shown in Figure 4. Assume ideal diode model, f = 500 Hz, R1 = 1 kΩ, RL = 1 MΩ and C = 0.01 μF.
(a) Verify the conditions for successful clamper operation.
(b) Determine the output waveform vL(t).
(c) Sketch the output voltage waveform vL(t). vin(t) (V)
Q5 Clamper Circuit (non-assessable problem)
Figure 4: The circuit for Question 4.
Consider the circuit shown in Figure 5. Assume ideal diode model and conditions for successful clamper operation are satisfied.
(a) Determine the output waveform vL(t).
(b) Sketch the output voltage waveform vL(t).
Week 10 Problems
vin(t) (V) C R1
Figure 5: The circuit for Question 5.
AUSTRALIAN NATIONAL UNIVERSITY Research School of Engineering
ENGN 1218 Introduction to Electronics Week 10 Problems with Solutions: Clipper Circuits
Complete Solution
The given circuits is a Biased parallel clipper.
vin(t) (V) 10
The sketch of input voltage is
Given that R1 = 1 kΩ and RL = 15 kΩ. As RL ≥ 10R1, we can ignore the voltage drop across R1.
For 0 < t < t1 and t2 < t < T
We see that the n-side of the diode is more +ve with respect to the p-side of the diode. Hence, the diode is reverse biased and acts as open circuit. The equivalent circuit when diode is reverse biased is
Week 10 Problems page 3
The output voltage is then
vL(t) = vin(t)
For t1 < t < t2
We see that the p-side of the diode is more +ve with respect to the n-side of the diode. Hence, the diode is forward biased and acts as short circuit. The equivalent circuit when diode is forward biased is
The output voltage is then vL(t) = −3V
The sketch of input and output voltages is shown below
Input v (t) in
Output v (t) L
Verify using PSPICE.
Week 10 Problems
Figure 6: The solution for Question 1.
Complete Solution
The given circuits is a Biased parallel clipper.
vin(t) (V)
First we replace the Si diode with ideal diode in series with 0.7V battery.
vin(t) 0.7V 6V
Combining the batteries, the simplified circuit is
Given that R1 = 1 kΩ and RL = 2 kΩ. As RL 10R1, we cannot ignore the voltage drop across R1.
For 0 < t < T2
We see that for the entire duration, the p-side of the diode is more +ve with respect to n-side of the diode.
Hence, the diode is forward biased and acts as short circuit. The equivalent circuit when diode is forward biased is
Week 10 Problems page 5
The output voltage is vL(t) = 6.7V
For T2 < t < T
We see that the n-side of the diode is more +ve with respect to p-side of the diode. Hence, the diode is reverse biased and acts as open circuit. The equivalent circuit when diode is reverse biased is
vin(t) = 1vin(t) 3
The output voltage is
vL(t) = RL R1 + RL
The sketch of input and output voltages is shown below
Input v (t) in
Output v (t) L
0 T/2 T 0 T/2 T
Figure 7: The input for Question 2. Verify using PSPICE.
Figure 8: The solution for Question 2.
Week 10 Problems
Q3 (challenge problem) Solution
The given circuits is
vin(t) (V) 10
The sketch of input and output voltages is shown below
Input v (t) in
Output v (t) L
Week 10 Problems
Figure 9: The solution for Question 3.
Q4 Clamper Circuit (non-assessable problem) Complete Solution
The given circuits is an unbiased clamper circuit.
vin(t) (V) 20
Giventhat f =500Hz,R1 =1kΩ,RL =1MΩandC=0.1μF.Wehave T = 1=2ms
5R1C = 0.05 ms << T2 5(R1+RL)C = 50.05ms>>T2
The three conditions are:-
(i) RL >> 10R1 so we can ignore the voltage drop across R1. (ii)5R1C<
During the +ve half of first cycle, the diode is forward biased and the capacitor is charged to 20V with polarity shown.
During the -ve half of first cycle, the diode is reverse biased. The capacitor cannot discharge through resistor and it retains its charge.
Week 10 Problems page 8
After the first cycle, the capacitor is charged and can be replaced by a dc voltage source in series with input voltage source as shown.
The output voltage is vL(t) = vin(t) − 20
The sketch of input and output voltages is shown below
40 30 20 10
0 −10 −20 −30 −40
Input v (t) in
Output v (t) L
Verify using PSPICE.
Week 10 Problems
Figure 10: The solution for Q4.
Q5 Clamper Circuit (non-assessable problem) Solution
The sketch of input and output voltages is shown below
Input v (t) in
Output v (t) L
Week 10 Problems
Figure 11: The solution for Q5.